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-rwxr-xr-xdebug/gdbserver.py2
-rw-r--r--debug/targets/RISC-V/spike-multi.py2
-rw-r--r--debug/targets/RISC-V/spike32-2-hwthread.py2
-rw-r--r--debug/targets/RISC-V/spike32-2.py2
-rw-r--r--debug/targets/RISC-V/spike32.py2
-rw-r--r--debug/targets/RISC-V/spike64-2-hwthread.py4
-rw-r--r--debug/targets/RISC-V/spike64-2-rtos.py2
-rw-r--r--debug/targets/RISC-V/spike64-2.py2
-rw-r--r--debug/targets/RISC-V/spike64.py2
-rw-r--r--debug/testlib.py6
-rw-r--r--isa/rv64mi/ma_addr.S7
11 files changed, 20 insertions, 13 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 603861d..2a97ccb 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -1416,7 +1416,7 @@ class TriggerDmode(TriggerTest):
i = 0
for i in range(16):
tdata1 = self.gdb.p(f"(({xlen_type} *)&data)[{2*i}]")
- if tdata1 == 0:
+ if (tdata1 == 0) or (tdata1 >> (self.hart.xlen-4) == 15):
break
tdata2 = self.gdb.p(f"(({xlen_type} *)&data)[{2*i+1}]")
diff --git a/debug/targets/RISC-V/spike-multi.py b/debug/targets/RISC-V/spike-multi.py
index 02be763..19f8d6c 100644
--- a/debug/targets/RISC-V/spike-multi.py
+++ b/debug/targets/RISC-V/spike-multi.py
@@ -11,7 +11,7 @@ class multispike(targets.Target):
spike64.spike64_hart(misa=0x8000000000341129, system=1),
spike64.spike64_hart(misa=0x8000000000341129, system=1)]
openocd_config_path = "spike-multi.cfg"
- timeout_sec = 30
+ timeout_sec = 180
server_timeout_sec = 120
implements_custom_test = True
support_hasel = False
diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py
index b617be2..3be3332 100644
--- a/debug/targets/RISC-V/spike32-2-hwthread.py
+++ b/debug/targets/RISC-V/spike32-2-hwthread.py
@@ -7,7 +7,7 @@ class spike32_2(targets.Target):
harts = [spike32.spike32_hart(misa=0x40341129),
spike32.spike32_hart(misa=0x40341129)]
openocd_config_path = "spike-2-hwthread.cfg"
- timeout_sec = 5
+ timeout_sec = 180
implements_custom_test = True
support_memory_sampling = False # not supported without sba
support_unavailable_control = True
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index 1d0cc48..0d5f19e 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -7,7 +7,7 @@ class spike32_2(targets.Target):
harts = [spike32.spike32_hart(misa=0x40141125),
spike32.spike32_hart(misa=0x40141125)]
openocd_config_path = "spike-2.cfg"
- timeout_sec = 30
+ timeout_sec = 180
implements_custom_test = True
support_unavailable_control = True
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index f0afd88..a196792 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -13,7 +13,7 @@ class spike32_hart(targets.Hart):
class spike32(targets.Target):
harts = [spike32_hart(misa=0x4034112d)]
openocd_config_path = "spike-1.cfg"
- timeout_sec = 30
+ timeout_sec = 180
implements_custom_test = True
support_memory_sampling = False # Needs SBA
freertos_binary = "bin/RTOSDemo32.axf"
diff --git a/debug/targets/RISC-V/spike64-2-hwthread.py b/debug/targets/RISC-V/spike64-2-hwthread.py
index d1d2bf7..4d6e4ba 100644
--- a/debug/targets/RISC-V/spike64-2-hwthread.py
+++ b/debug/targets/RISC-V/spike64-2-hwthread.py
@@ -7,9 +7,7 @@ class spike64_2(targets.Target):
harts = [spike64.spike64_hart(misa=0x8000000000341129),
spike64.spike64_hart(misa=0x8000000000341129)]
openocd_config_path = "spike-2-hwthread.cfg"
- # Increased timeout because we use abstract_rti to artificially slow things
- # down.
- timeout_sec = 20
+ timeout_sec = 180
implements_custom_test = True
support_hasel = False
support_memory_sampling = False # Needs SBA
diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py
index f4de8b8..0b87391 100644
--- a/debug/targets/RISC-V/spike64-2-rtos.py
+++ b/debug/targets/RISC-V/spike64-2-rtos.py
@@ -7,7 +7,7 @@ class spike64_2_rtos(targets.Target):
harts = [spike64.spike64_hart(misa=0x8000000000141129),
spike64.spike64_hart(misa=0x8000000000141129)]
openocd_config_path = "spike-rtos.cfg"
- timeout_sec = 60
+ timeout_sec = 180
implements_custom_test = True
support_hasel = False
test_semihosting = False
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index e4c7524..ea31636 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -7,7 +7,7 @@ class spike64_2(targets.Target):
harts = [spike64.spike64_hart(misa=0x8000000000141129),
spike64.spike64_hart(misa=0x8000000000141129)]
openocd_config_path = "spike-2.cfg"
- timeout_sec = 5
+ timeout_sec = 180
implements_custom_test = True
support_memory_sampling = False # Needs SBA
support_unavailable_control = True
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index 8f5ba4f..5616977 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -14,7 +14,7 @@ class spike64_hart(targets.Hart):
class spike64(targets.Target):
harts = [spike64_hart()]
openocd_config_path = "spike-1.cfg"
- timeout_sec = 30
+ timeout_sec = 180
implements_custom_test = True
freertos_binary = "bin/RTOSDemo64.axf"
support_unavailable_control = True
diff --git a/debug/testlib.py b/debug/testlib.py
index 1d3fd18..d4826bb 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -1076,12 +1076,16 @@ class PrivateState:
def load_excluded_tests(excluded_tests_file, target_name):
result = []
- if excluded_tests_file is None or len(excluded_tests_file) == 0:
+ if excluded_tests_file is None:
+ # No list of excluded tests was specified
return result
target_excludes = {}
with open(excluded_tests_file, encoding="utf-8") as file:
raw_data = yaml.safe_load(file)
+ if raw_data is None:
+ # File contains no targets
+ return result
for (target, test_list) in raw_data.items():
if not isinstance(test_list, list):
raise ValueError(
diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index f02a1af..8579c01 100644
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -20,6 +20,7 @@ RVTEST_CODE_BEGIN
# indicate it's a load test
li s1, CAUSE_MISALIGNED_LOAD
+ li s2, CAUSE_LOAD_ACCESS
#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1)))
@@ -56,6 +57,7 @@ RVTEST_CODE_BEGIN
# indicate it's a store test
li s1, CAUSE_MISALIGNED_STORE
+ li s2, CAUSE_STORE_ACCESS
/* Check that a misaligned store has some effect and takes no exception,
or takes no effect and generates an exception. This is not very
@@ -96,7 +98,10 @@ RVTEST_CODE_BEGIN
.global mtvec_handler
mtvec_handler:
csrr t0, mcause
- bne t0, s1, fail
+ beq t0, s1, 1f
+ beq t0, s2, 1f
+ j fail
+1:
csrr t0, mbadaddr
beqz t0, 1f
generated by cgit v1.1 at 2024-06-28 11:34:52 +0000