diff options
106 files changed, 5525 insertions, 101 deletions
diff --git a/.github/workflows/debug.yml b/.github/workflows/debug.yml index 29ca5b2..7b6beb4 100644 --- a/.github/workflows/debug.yml +++ b/.github/workflows/debug.yml @@ -1,6 +1,9 @@ -on: pull_request +on: + pull_request: + paths: + - 'debug/**' -name: Check Code Style (checkpatch) +name: Check Debug Code Style (pylint) jobs: check: diff --git a/.github/workflows/spike-openocd-tests.yml b/.github/workflows/spike-openocd-tests.yml new file mode 100644 index 0000000..577bd95 --- /dev/null +++ b/.github/workflows/spike-openocd-tests.yml @@ -0,0 +1,172 @@ +# Build Spike and run a couple of debug tests. + +name: Test OpenOCD against 2 spike configurations + +env: + SPIKE_REPO: https://github.com/riscv-software-src/riscv-isa-sim.git + SPIKE_REV: master + RISCV_TESTS_REPO: https://github.com/riscv-software-src/riscv-tests.git + RISCV_TESTS_REV: master + OPENOCD_REPO: https://github.com/riscv/riscv-openocd.git + OPENOCD_REV: riscv + TOOLCHAIN_URL: https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v12.2.0-1/xpack-riscv-none-elf-gcc-12.2.0-1-linux-x64.tar.gz + +on: + # Run on merges to master to populate the cache with entities that are + # accessible by every pull request. + push: + branches: + - riscv + paths: + - 'debug/**' + - '.github/workflows/spike-openocd-tests.yml' + pull_request: + types: [synchronize, opened, reopened] + paths: + - 'debug/**' + - '.github/workflows/spike-openocd-tests.yml' + +# There is some commented out code below that would be useful in adding this +# workflow to other repos. Ideally we can come up with something that would +# leave this file almost identical between repos, so they can all easily run +# this test suite. + +jobs: + test: + name: Test debug (Ubuntu) + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v3 + with: + submodules: recursive + + - name: Install packages + run: | + sudo apt-get update + sudo apt-get install -y device-tree-compiler build-essential + + - name: Get revisions of dependencies + run: | + SPIKE_COMMIT=$( git ls-remote "$SPIKE_REPO" $SPIKE_REV | awk '{ print $1; }' ) + OPENOCD_COMMIT=$( git ls-remote "$OPENOCD_REPO" $OPENOCD_REV | awk '{ print $1; }' ) + echo "Revison of Spike: $SPIKE_COMMIT" + echo "Revision of OpenOCD: $OPENOCD_COMMIT" + # Save for later use + echo "SPIKE_COMMIT=$SPIKE_COMMIT" >> $GITHUB_ENV + echo "OPENOCD_COMMIT=$OPENOCD_COMMIT" >> $GITHUB_ENV + + - name: Get the toolchain from cache (if available) + id: cache-restore-toolchain + uses: actions/cache/restore@v3 + with: + path: /opt/riscv/toolchain + key: "toolchain-${{env.TOOLCHAIN_URL}}" + + - if: ${{ steps.cache-restore-toolchain.outputs.cache-hit != 'true' }} + name: Download Toolchain (if not cached) + run: | + mkdir -p /opt/riscv/toolchain + wget --progress=dot:giga $TOOLCHAIN_URL -O /tmp/toolchain.tar.gz + + - if: ${{ steps.cache-restore-toolchain.outputs.cache-hit != 'true' }} + name: Install Toolchain (if not cached) + run: tar zxf /tmp/toolchain.tar.gz --strip-components=1 -C /opt/riscv/toolchain + + - name: Save the toolchain to the cache (if necessary) + id: cache-save-toolchain + uses: actions/cache/save@v3 + with: + path: /opt/riscv/toolchain + key: "toolchain-${{env.TOOLCHAIN_URL}}" + + - name: Get OpenOCD from cache (if available) + id: cache-restore-openocd + uses: actions/cache/restore@v3 + with: + path: /opt/riscv/openocd + key: "openocd-${{env.OPENOCD_COMMIT}}" + + - if: ${{ steps.cache-restore-openocd.outputs.cache-hit != 'true' }} + name: Download OpenOCD source (if not cached) + run: | + git clone "$OPENOCD_REPO" + cd riscv-openocd + git checkout "$OPENOCD_COMMIT" + git submodule update --init --recursive + + - if: ${{ steps.cache-restore-openocd.outputs.cache-hit != 'true' }} + name: Build OpenOCD (if not cached) + run: | + cd riscv-openocd + ./bootstrap + ./configure --prefix=/opt/riscv/openocd + make -j"$(nproc 2> /dev/null || sysctl -n hw.ncpu)" + make install + + - if: ${{ steps.cache-restore-openocd.outputs.cache-hit != 'true' }} + name: Save OpenOCD to cache (if built) + id: cache-save-openocd + uses: actions/cache/save@v3 + with: + path: /opt/riscv/openocd + key: "openocd-${{env.OPENOCD_COMMIT}}" + + - name: Get spike from cache (if available) + id: cache-restore-spike + uses: actions/cache/restore@v3 + with: + path: /opt/riscv/spike + key: "spike-${{env.SPIKE_COMMIT}}" + + - if: ${{ steps.cache-restore-spike.outputs.cache-hit != 'true' }} + name: Download Spike source (if not cached) + run: | + git clone "$SPIKE_REPO" + cd riscv-isa-sim + git checkout "$SPIKE_COMMIT" + git submodule update --init --recursive + + - if: ${{ steps.cache-restore-spike.outputs.cache-hit != 'true' }} + name: Build Spike (if not cached) + run: | + cd riscv-isa-sim + mkdir build && cd build + ../configure --prefix=/opt/riscv/spike + make -j"$(nproc 2> /dev/null || sysctl -n hw.ncpu)" + make install + + - if: ${{ steps.cache-restore-spike.outputs.cache-hit != 'true' }} + name: Save spike to cache (if built) + id: cache-save-spike + uses: actions/cache/save@v3 + with: + path: /opt/riscv/spike + key: "spike-${{env.SPIKE_COMMIT}}" + + - name: Run Spike32 Tests + id: spike32-tests + run: | + cd debug + ./gdbserver.py targets/RISC-V/spike32.py --print-failures \ + --gcc /opt/riscv/toolchain/bin/riscv-none-elf-gcc \ + --gdb /opt/riscv/toolchain/bin/riscv-none-elf-gdb \ + --sim_cmd /opt/riscv/spike/bin/spike \ + --server_cmd /opt/riscv/openocd/bin/openocd + + - name: Run Spike64-2 Tests + if: success() || steps.spike32-tests.conclusion == 'failure' + run: | + cd debug + ./gdbserver.py targets/RISC-V/spike64-2.py --print-failures \ + --gcc /opt/riscv/toolchain/bin/riscv-none-elf-gcc \ + --gdb /opt/riscv/toolchain/bin/riscv-none-elf-gdb \ + --sim_cmd /opt/riscv/spike/bin/spike \ + --server_cmd /opt/riscv/openocd/bin/openocd + + - name: Archive test logs + # Proceed even if there was a failed test + if: ${{ success() || failure() }} + uses: actions/upload-artifact@v3 + with: + name: test-logs + path: riscv-tests/debug/logs diff --git a/debug/README.md b/debug/README.md index b98d8c2..6dc30d7 100644 --- a/debug/README.md +++ b/debug/README.md @@ -19,6 +19,7 @@ The following should be in the user's path: * openocd (can be overridden with `--server_cmd` when running gdbserver.py manually), which should be the latest from https://github.com/riscv/riscv-openocd.git. +* Python packages that might not be installed: pexpect Usage ===== diff --git a/debug/gdbserver.py b/debug/gdbserver.py index ff0f7ab..f00dcc9 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -11,6 +11,7 @@ import os import re import itertools +from datetime import datetime import targets import testlib from testlib import assertEqual, assertNotEqual @@ -19,7 +20,8 @@ from testlib import assertGreater, assertRegex, assertLess from testlib import GdbTest, GdbSingleHartTest, TestFailed from testlib import TestNotApplicable, CompileError from testlib import UnknownThread -from testlib import CouldNotReadRegisters +from testlib import CouldNotReadRegisters, CommandException +from testlib import ThreadTerminated MSTATUS_UIE = 0x00000001 MSTATUS_SIE = 0x00000002 @@ -220,14 +222,15 @@ class CustomRegisterTest(SimpleRegisterTest): class SimpleNoExistTest(GdbTest): def test(self): + nonexist_csr = self.hart.nonexist_csr try: - self.gdb.p("$csr2288") - assert False, "Reading csr2288 should have failed" + self.gdb.p(f"${nonexist_csr}") + assert False, f"Reading the ${nonexist_csr} should have failed" except testlib.CouldNotFetch: pass try: - self.gdb.p("$csr2288=5") - assert False, "Writing csr2288 should have failed" + self.gdb.p(f"${nonexist_csr}=5") + assert False, f"Writing the ${nonexist_csr} should have failed" except testlib.CouldNotFetch: pass @@ -911,7 +914,7 @@ class RepeatReadTest(DebugTest): def test(self): self.gdb.b("main:start") self.gdb.c() - mtime_addr = 0x02000000 + 0xbff8 + mtime_addr = self.target.clint_addr + 0xbff8 count = 1024 output = self.gdb.command( f"monitor riscv repeat_read {count} 0x{mtime_addr:x} 4") @@ -1034,15 +1037,17 @@ class InterruptTest(GdbSingleHartTest): local = self.gdb.p("local") if interrupt_count > 1000 and \ local > 1000: + self.disable_timer() return + self.disable_timer() assertGreater(interrupt_count, 1000) assertGreater(local, 1000) def postMortem(self): GdbSingleHartTest.postMortem(self) - self.gdb.p("*((long long*) 0x200bff8)") - self.gdb.p("*((long long*) 0x2004000)") + self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0xbff8:x})") + self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0x4000:x})") self.gdb.p("interrupt_count") self.gdb.p("local") @@ -1186,6 +1191,8 @@ class MulticoreRunAllHaltOne(GdbTest): time.sleep(1) self.gdb.p("buf", fmt="") + self.disable_timer(interrupt=True) + class MulticoreRtosSwitchActiveHartTest(GdbTest): compile_args = ("programs/multicore.c", "-DMULTICORE") @@ -1215,6 +1222,8 @@ class MulticoreRtosSwitchActiveHartTest(GdbTest): assertIn("set_trap_handler", output) assertNotIn("received signal SIGTRAP", output) + self.disable_timer() + class SmpSimultaneousRunHalt(GdbTest): compile_args = ("programs/run_halt_timing.S", "-DMULTICORE") @@ -1403,7 +1412,7 @@ class TriggerDmode(TriggerTest): i = 0 for i in range(16): tdata1 = self.gdb.p(f"(({xlen_type} *)&data)[{2*i}]") - if tdata1 == 0: + if (tdata1 == 0) or (tdata1 >> (self.hart.xlen-4) == 15): break tdata2 = self.gdb.p(f"(({xlen_type} *)&data)[{2*i+1}]") @@ -1557,6 +1566,7 @@ class DownloadTest(GdbTest): # assertIn("0xbead", output) class PrivTest(GdbSingleHartTest): + """Base class for a few tests that change privilege levels.""" compile_args = ("programs/priv.S", ) def setup(self): # pylint: disable=attribute-defined-outside-init @@ -1583,8 +1593,8 @@ class PrivTest(GdbSingleHartTest): pass class PrivRw(PrivTest): + """Test reading/writing priv.""" def test(self): - """Test reading/writing priv.""" self.write_nop_program(4) for privilege in range(4): self.gdb.p(f"$priv={privilege}") @@ -1595,9 +1605,9 @@ class PrivRw(PrivTest): assertEqual(actual, privilege) class PrivChange(PrivTest): + """Test that the core's privilege level actually changes when the debugger + writes it.""" def test(self): - """Test that the core's privilege level actually changes.""" - if 0 not in self.supported: raise TestNotApplicable @@ -1666,6 +1676,10 @@ class TranslateTest(GdbSingleHartTest): assertEqual(0xdeadbeef, self.gdb.p("virtual[0]")) assertEqual(0x55667788, self.gdb.p("virtual[1]")) + # disable mmu + self.gdb.p("$mstatus=$mstatus & ~0x20000") + self.gdb.p("$satp=0") + SATP_MODE_OFF = 0 SATP_MODE_SV32 = 1 SATP_MODE_SV39 = 8 @@ -1803,22 +1817,28 @@ class EbreakTest(GdbSingleHartTest): output = self.gdb.c() assertIn("_exit", output) -class CeaseMultiTest(GdbTest): - """Test that we work correctly when a hart ceases to respond (e.g. because +class UnavailableMultiTest(GdbTest): + """Test that we work correctly when a hart becomes unavailable (e.g. because it's powered down).""" compile_args = ("programs/counting_loop.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE") def early_applicable(self): - return self.hart.support_cease and len(self.target.harts) > 1 + return (self.hart.support_cease or + self.target.support_unavailable_control) \ + and len(self.target.harts) > 1 def setup(self): ProgramTest.setup(self) - self.parkOtherHarts("precease") + self.parkOtherHarts() def test(self): # Run all the way to the infinite loop in exit - self.gdb.c(wait=False) + self.gdb.c_all(wait=False) + # Other hart should have become unavailable. + if self.target.support_unavailable_control: + self.server.wait_until_running(self.target.harts) + self.server.set_available([self.hart]) self.gdb.expect(r"\S+ became unavailable.") self.gdb.interrupt() @@ -1830,7 +1850,7 @@ class CeaseMultiTest(GdbTest): self.gdb.p("$misa") assert False, \ "Shouldn't be able to access unavailable hart." - except UnknownThread: + except (UnknownThread, CommandException): pass # Check that the main hart can still be debugged. @@ -1845,6 +1865,7 @@ class CeaseMultiTest(GdbTest): self.gdb.p("$pc=_start") self.exit() + class CeaseStepiTest(ProgramTest): """Test that we work correctly when the hart we're debugging ceases to respond.""" @@ -1868,11 +1889,12 @@ class CeaseStepiTest(ProgramTest): except CouldNotReadRegisters: pass -class CeaseRunTest(ProgramTest): +class UnavailableRunTest(ProgramTest): """Test that we work correctly when the hart we're debugging ceases to respond.""" def early_applicable(self): - return self.hart.support_cease + return self.hart.support_cease or \ + self.target.support_unavailable_control def test(self): self.gdb.b("main") @@ -1880,10 +1902,23 @@ class CeaseRunTest(ProgramTest): assertIn("Breakpoint", output) assertIn("main", output) - self.gdb.p("$pc=precease") + if self.target.support_unavailable_control: + self.gdb.p("$pc=loop_forever") + else: + self.gdb.p("$pc=cease") self.gdb.c(wait=False) + if self.target.support_unavailable_control: + self.server.wait_until_running([self.hart]) + self.server.set_available( + [h for h in self.target.harts if h != self.hart]) self.gdb.expect(r"\S+ became unavailable.") self.gdb.interrupt() + # gdb might automatically switch to the available hart. + try: + self.gdb.select_hart(self.hart) + except ThreadTerminated: + # GDB sees that the thread is gone. Count this as success. + return try: self.gdb.p("$pc") assert False, ("Registers shouldn't be accessible when the hart is " @@ -1891,6 +1926,93 @@ class CeaseRunTest(ProgramTest): except CouldNotReadRegisters: pass +class UnavailableCycleTest(ProgramTest): + """Test that harts can be debugged after becoming temporarily + unavailable.""" + def early_applicable(self): + return self.target.support_unavailable_control + + def test(self): + self.gdb.b("main") + output = self.gdb.c() + assertIn("Breakpoint", output) + assertIn("main", output) + + self.gdb.p("$pc=loop_forever") + self.gdb.c(wait=False) + self.server.wait_until_running([self.hart]) + self.server.set_available( + [h for h in self.target.harts if h != self.hart]) + self.gdb.expect(r"\S+ became unavailable.") + + # Now send a DMI command through OpenOCD to make the hart available + # again. + + self.server.set_available(self.target.harts) + self.gdb.expect(r"\S+ became available") + self.gdb.interrupt() + self.gdb.p("$pc") + +class UnavailableHaltedTest(ProgramTest): + """Test behavior when the current hart becomes unavailable while halted.""" + def early_applicable(self): + return self.target.support_unavailable_control + + def test_resume(self, c_expect=None): + # Confirm things don't completely fall apart on `c` + self.gdb.c(wait=False) + if c_expect: + self.gdb.expect(c_expect) + else: + time.sleep(1) + + # Now send a DMI command through OpenOCD to make the hart available + # again. + self.server.set_available(self.target.harts) + + # The hart will show up as halted. That's just how spike behaves when we + # make a hart unavailable while it's halted. + + self.gdb.expect("became available") + self.gdb.p("$minstret") + + def test(self): + self.gdb.b("main") + output = self.gdb.c() + assertIn("Breakpoint", output) + assertIn("main", output) + + self.server.set_available( + [h for h in self.target.harts if h != self.hart]) + self.gdb.command(f"# disabled hart {self.hart.id}") + # gdb won't show that the hart became unavailable, because it thinks + # nothing can changed on a halted Linux thread. + try: + # We can't try this with something reasonable like $pc, because gdb + # has cached it, and it assumes the target can't change while it's + # halted. + self.gdb.p("$minstret") + assert False, ("Registers shouldn't be accessible when the hart is " + "unavailable.") + except testlib.CouldNotFetch: + pass + + # There's a breakpoint set, so gdb will single step. You can't single + # step an unavailable target, so gdb should get a message to that + # effect. + self.test_resume(c_expect="unavailable") + + # Delete breakpoints + self.gdb.command("delete") + self.server.set_available( + [h for h in self.target.harts if h != self.hart]) + + # Resume again. With breakpoints cleared, gdb will send vCont;c instead + # of step. There should be no error this time, since there is no + # observable difference between an unavailable thread and a running + # thread. + self.test_resume() + class FreeRtosTest(GdbTest): def early_applicable(self): return self.target.freertos_binary @@ -1985,7 +2107,6 @@ class EtriggerTest(DebugTest): self.gdb.b("handle_trap") def test(self): - self.gdb.command(f"monitor targets {self.hart.id}") # Set trigger on Load access fault self.gdb.command("monitor riscv etrigger set m 0x20") # Set fox to a null pointer so we'll get a load access exception later. @@ -2005,17 +2126,21 @@ class IcountTest(DebugTest): DebugTest.setup(self) self.gdb.b("main") self.gdb.c() - self.gdb.command(f"monitor targets {self.hart.id}") def test(self): # Execute 2 instructions. output = self.gdb.command("monitor riscv icount set m 2") - assertNotIn("Failed", output) + if self.target.icount_limit > 1: + assertNotIn("Failed", output) + else: + assertIn("Failed", output) + self.gdb.b("main_post_csrr") output = self.gdb.c() - assertIn("breakpoint", output) + assertIn("main_post_csrr", output) main_post_csrr = self.gdb.p("&main_post_csrr") assertEqual(self.gdb.p("$pc"), main_post_csrr) + self.gdb.command("delete") self.gdb.command("monitor riscv icount clear") # Execute 1 instruction. @@ -2035,7 +2160,6 @@ class ItriggerTest(GdbSingleHartTest): self.gdb.load() def test(self): - self.gdb.command(f"monitor targets {self.hart.id}") output = self.gdb.command("monitor riscv itrigger set 0x80") assertIn("Doesn't make sense", output) output = self.gdb.command("monitor riscv itrigger set m 0") @@ -2072,6 +2196,14 @@ def main(): module = sys.modules[__name__] + # initialize PRNG + selected_seed = parsed.seed + if parsed.seed is None: + selected_seed = int(datetime.now().timestamp()) + print(f"PRNG seed for {target.name} is generated automatically") + print(f"PRNG seed for {target.name} is {selected_seed}") + random.seed(selected_seed) + return testlib.run_all_tests(module, target, parsed) # TROUBLESHOOTING TIPS diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 09cad53..5c281a6 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -84,8 +84,9 @@ handle_reset: beq t0, t1, 1b .p2align 2 2: - # Restore mtvec + # Restore mtvec and mstatus csrw mtvec, t2 + csrwi mstatus, 0 #ifdef MULTICORE csrr t0, CSR_MHARTID diff --git a/debug/programs/init.h b/debug/programs/init.h index 06d5384..e79681d 100644 --- a/debug/programs/init.h +++ b/debug/programs/init.h @@ -1,8 +1,10 @@ #ifndef INIT_H #define INIT_H -#define MTIME (*(volatile long long *)(0x02000000 + 0xbff8)) -#define MTIMECMP ((volatile long long *)(0x02000000 + 0x4000)) +#ifdef CLINT +#define MTIME (*(volatile long long *)(CLINT + 0xbff8)) +#define MTIMECMP ((volatile long long *)(CLINT + 0x4000)) +#endif typedef void* (*trap_handler_t)(unsigned hartid, unsigned mcause, void *mepc, void *sp); diff --git a/debug/programs/run_halt_timing.S b/debug/programs/run_halt_timing.S index ce4000a..dc5d58b 100644 --- a/debug/programs/run_halt_timing.S +++ b/debug/programs/run_halt_timing.S @@ -8,10 +8,14 @@ # define REGBYTES 4 #endif +#ifdef CLINT +#define MTIME_ADDR CLINT + 0xbff8 +#endif + .global main main: li s0, 0 - li s1, 0x0200bff8 + li s1, MTIME_ADDR loop: addi s0, s0, 1 LREG s2, 0(s1) diff --git a/debug/programs/translate.c b/debug/programs/translate.c index 59dffd6..e246baf 100644 --- a/debug/programs/translate.c +++ b/debug/programs/translate.c @@ -163,6 +163,7 @@ int main() virtual = (uint32_t *) ( (reg_t) virtual | ~(((reg_t) 1 << vms->vaddr_bits) - 1)); add_entry(master_table, 0, (reg_t) virtual, (reg_t) physical); + __asm__ __volatile__ ("sfence.vma" ::: "memory"); // Virtual memory synchronization unsigned long satp = set_field(0, SATP_MODE, vms->mode); satp = set_field(satp, SATP_PPN, ((unsigned long) master_table) >> 12); diff --git a/debug/targets.py b/debug/targets.py index 1952749..bb7a5cf 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -33,6 +33,9 @@ class Hart: # no device mapped to that location. bad_address = None + # The non-existent register for access test + nonexist_csr = "csr2288" + # Number of instruction triggers the hart supports. instruction_hardware_breakpoint_count = 0 @@ -93,9 +96,12 @@ class Target: # before starting the test. gdb_setup = [] - # Supports mtime at 0x2004000 + # Supports mtime default at clint_addr + 0x4000 supports_clint_mtime = True + # CLINT register address, set to the default value of spike. + clint_addr = 0x02000000 + # Implements custom debug registers like spike does. It seems unlikely any # hardware will every do that. implements_custom_test = False @@ -129,6 +135,12 @@ class Target: # in https://github.com/FreeRTOS/FreeRTOS. freertos_binary = None + # Supports controlling hart availability through DMCUSTOM. + support_unavailable_control = False + + # Instruction count limit + icount_limit = 4 + # Internal variables: directory = None temporary_files = [] @@ -186,6 +198,7 @@ class Target: Target.temporary_files.append(self.temporary_binary) args = list(sources) + [ + f"-DCLINT={self.clint_addr}", "programs/entry.S", "programs/init.c", f"-DNHARTS={len(self.harts)}", "-I", "../env", diff --git a/debug/targets/RISC-V/spike-multi.py b/debug/targets/RISC-V/spike-multi.py index 02be763..19f8d6c 100644 --- a/debug/targets/RISC-V/spike-multi.py +++ b/debug/targets/RISC-V/spike-multi.py @@ -11,7 +11,7 @@ class multispike(targets.Target): spike64.spike64_hart(misa=0x8000000000341129, system=1), spike64.spike64_hart(misa=0x8000000000341129, system=1)] openocd_config_path = "spike-multi.cfg" - timeout_sec = 30 + timeout_sec = 180 server_timeout_sec = 120 implements_custom_test = True support_hasel = False diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py index 3a24269..3be3332 100644 --- a/debug/targets/RISC-V/spike32-2-hwthread.py +++ b/debug/targets/RISC-V/spike32-2-hwthread.py @@ -7,9 +7,10 @@ class spike32_2(targets.Target): harts = [spike32.spike32_hart(misa=0x40341129), spike32.spike32_hart(misa=0x40341129)] openocd_config_path = "spike-2-hwthread.cfg" - timeout_sec = 5 + timeout_sec = 180 implements_custom_test = True support_memory_sampling = False # not supported without sba + support_unavailable_control = True def create(self): return testlib.Spike(self, isa="RV32IMAFDV", support_hasel=True, diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index 6a5a839..0d5f19e 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -7,8 +7,9 @@ class spike32_2(targets.Target): harts = [spike32.spike32_hart(misa=0x40141125), spike32.spike32_hart(misa=0x40141125)] openocd_config_path = "spike-2.cfg" - timeout_sec = 30 + timeout_sec = 180 implements_custom_test = True + support_unavailable_control = True def create(self): return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4, diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index 0d67ebd..a196792 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -13,10 +13,11 @@ class spike32_hart(targets.Hart): class spike32(targets.Target): harts = [spike32_hart(misa=0x4034112d)] openocd_config_path = "spike-1.cfg" - timeout_sec = 30 + timeout_sec = 180 implements_custom_test = True support_memory_sampling = False # Needs SBA freertos_binary = "bin/RTOSDemo32.axf" + support_unavailable_control = True def create(self): # 64-bit FPRs on 32-bit target diff --git a/debug/targets/RISC-V/spike64-2-hwthread.py b/debug/targets/RISC-V/spike64-2-hwthread.py index 1ac184a..4d6e4ba 100644 --- a/debug/targets/RISC-V/spike64-2-hwthread.py +++ b/debug/targets/RISC-V/spike64-2-hwthread.py @@ -7,12 +7,11 @@ class spike64_2(targets.Target): harts = [spike64.spike64_hart(misa=0x8000000000341129), spike64.spike64_hart(misa=0x8000000000341129)] openocd_config_path = "spike-2-hwthread.cfg" - # Increased timeout because we use abstract_rti to artificially slow things - # down. - timeout_sec = 20 + timeout_sec = 180 implements_custom_test = True support_hasel = False support_memory_sampling = False # Needs SBA + support_unavailable_control = True def create(self): return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30, diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py index 33c1ff2..0b87391 100644 --- a/debug/targets/RISC-V/spike64-2-rtos.py +++ b/debug/targets/RISC-V/spike64-2-rtos.py @@ -7,12 +7,13 @@ class spike64_2_rtos(targets.Target): harts = [spike64.spike64_hart(misa=0x8000000000141129), spike64.spike64_hart(misa=0x8000000000141129)] openocd_config_path = "spike-rtos.cfg" - timeout_sec = 60 + timeout_sec = 180 implements_custom_test = True support_hasel = False test_semihosting = False support_manual_hwbp = False # not supported with `-rtos riscv` support_memory_sampling = False # not supported with `-rtos riscv` + support_unavailable_control = True def create(self): return testlib.Spike(self, abstract_rti=30, support_hasel=False, diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index 48326ad..ea31636 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -7,9 +7,10 @@ class spike64_2(targets.Target): harts = [spike64.spike64_hart(misa=0x8000000000141129), spike64.spike64_hart(misa=0x8000000000141129)] openocd_config_path = "spike-2.cfg" - timeout_sec = 5 + timeout_sec = 180 implements_custom_test = True support_memory_sampling = False # Needs SBA + support_unavailable_control = True def create(self): return testlib.Spike(self) diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 79176c2..5616977 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -14,9 +14,10 @@ class spike64_hart(targets.Hart): class spike64(targets.Target): harts = [spike64_hart()] openocd_config_path = "spike-1.cfg" - timeout_sec = 30 + timeout_sec = 180 implements_custom_test = True freertos_binary = "bin/RTOSDemo64.axf" + support_unavailable_control = True def create(self): # 32-bit FPRs only diff --git a/debug/testlib.py b/debug/testlib.py index 2155e05..d4826bb 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -1,7 +1,6 @@ import collections import os import os.path -import random import re import shlex import subprocess @@ -10,6 +9,7 @@ import tempfile import time import traceback +import tty import pexpect import yaml @@ -294,6 +294,7 @@ class VcsSim: pass class Openocd: + # pylint: disable=too-many-instance-attributes # pylint: disable-next=consider-using-with logfile = tempfile.NamedTemporaryFile(prefix='openocd', suffix='.log') logname = logfile.name @@ -302,27 +303,22 @@ class Openocd: freertos=False, debug_openocd=False): self.timeout = timeout self.debug_openocd = debug_openocd + self.command_count = 0 if server_cmd: cmd = shlex.split(server_cmd) else: cmd = ["openocd"] - if debug: - cmd.append("-d") # This command needs to come before any config scripts on the command # line, since they are executed in order. cmd += [ # Tell OpenOCD to bind gdb to an unused, ephemeral port. - "--command", - "gdb_port 0", - # Disable tcl and telnet servers, since they are unused and because - # the port numbers will conflict if multiple OpenOCD processes are - # running on the same server. - "--command", - "tcl_port disabled", - "--command", - "telnet_port disabled", + "--command", "gdb_port 0", + # We create a socket for OpenOCD command line (TCL-RPC) + "--command", "tcl_port 0", + # don't use telnet + "--command", "telnet_port disabled", ] if config: @@ -332,6 +328,7 @@ class Openocd: sys.exit(1) cmd += ["-f", self.config_file] + if debug: cmd.append("-d") @@ -343,6 +340,9 @@ class Openocd: # pylint: disable-next=consider-using-with raw_logfile = open(Openocd.logname, "wb") + # pylint: disable-next=consider-using-with + self.read_log_fd = open(Openocd.logname, "rb") + self.log_buf = b"" try: # pylint: disable-next=consider-using-with spike_dasm = subprocess.Popen("spike-dasm", stdin=subprocess.PIPE, @@ -364,12 +364,18 @@ class Openocd: logfile.flush() self.gdb_ports = [] - self.process = self.start(cmd, logfile, extra_env) + self.tclrpc_port = None + self.start(cmd, logfile, extra_env) + + self.openocd_cli = pexpect.spawn(f"nc localhost {self.tclrpc_port}") + # TCL-RPC uses \x1a as a watermark for end of message. We set raw + # pty mode to disable translation of \x1a to EOF + tty.setraw(self.openocd_cli.child_fd) def start(self, cmd, logfile, extra_env): combined_env = {**os.environ, **extra_env} # pylint: disable-next=consider-using-with - process = subprocess.Popen(cmd, stdin=subprocess.PIPE, + self.process = subprocess.Popen(cmd, stdin=None, stdout=logfile, stderr=logfile, env=combined_env) try: @@ -377,38 +383,34 @@ class Openocd: # using OpenOCD to communicate with a simulator this may take a # long time, and gdb will time out when trying to connect if we # attempt too early. - start = time.time() - messaged = False - with open(Openocd.logname, "r", encoding='utf-8') as fd: - while True: - line = fd.readline() - if not line: - if not process.poll() is None: - raise TestLibError("OpenOCD exited early.") - time.sleep(0.1) - continue - - m = re.search( - r"Listening on port (\d+) for gdb connections", line) - if m: - self.gdb_ports.append(int(m.group(1))) - - if "telnet server disabled" in line: - break - - if not messaged and time.time() - start > 1: - messaged = True - print("Waiting for OpenOCD to start...") - if (time.time() - start) > self.timeout: - raise TestLibError("Timed out waiting for OpenOCD to " - "listen for gdb") + while True: + m = self.expect( + rb"Listening on port (?P<port>\d+) for " + rb"(?P<server>(?:gdb)|(?:tcl)) connections", + message="Waiting for OpenOCD to start up...") + if m["server"] == b"gdb": + self.gdb_ports.append(int(m["port"])) + elif m["server"] == b"tcl": + if self.tclrpc_port: + raise TestLibError( + "unexpected re-definition of TCL-RPC port") + self.tclrpc_port = int(m["port"]) + # WARNING! WARNING! WARNING! + # The condition below works properly only if OpenOCD reports + # gdb/tcl ports in a specific order. Namely, it requires the + # gdb ports to be reported before the tcl one. At the moment + # this comment was written OpenOCD reports these ports in the + # required order if we have a call to `init` statement in + # either target configuration file or command-line parameter. + # All configuration files used in testing include a call to + # `init` + if self.tclrpc_port and (len(self.gdb_ports) > 0): + break if self.debug_openocd: # pylint: disable=consider-using-with self.debugger = subprocess.Popen(["gnome-terminal", "-e", - f"gdb --pid={process.pid}"]) - return process - + f"gdb --pid={self.process.pid}"]) except Exception: print_log(Openocd.logname) raise @@ -434,6 +436,100 @@ class Openocd: return True return False + def command(self, cmd): + """Send the command to OpenOCD's TCL-RPC server. Return the output of + the command, minus the prompt.""" + self.openocd_cli.write(f"{cmd}\n\x1a") + self.openocd_cli.expect(rb"(.*)\x1a") + m = self.openocd_cli.match.group(1) + return m + + def expect(self, regex, message=None): + """Wait for the regex to match the log, and return the match object. If + message is given, print it while waiting. + We read the logfile to tell us what OpenOCD has done.""" + messaged = False + start = time.time() + + while True: + for line in self.read_log_fd.readlines(): + line = line.rstrip() + # Remove nulls, carriage returns, and newlines. + line = re.sub(rb"[\x00\r\n]+", b"", line) + # Remove debug messages. + debug_match = re.search(rb"Debug: \d+ \d+ .*", line) + if debug_match: + line = line[:debug_match.start()] + line[debug_match.end():] + self.log_buf += line + else: + self.log_buf += line + b"\n" + + m = re.search(regex, self.log_buf, re.MULTILINE | re.DOTALL) + if m: + self.log_buf = self.log_buf[m.end():] + return m + + if not self.process.poll() is None: + raise TestLibError("OpenOCD exited early.") + + if message and not messaged and time.time() - start > 1: + messaged = True + print(message) + + if (time.time() - start) > self.timeout: + raise TestLibError(f"Timed out waiting for {regex} in " + f"{Openocd.logname}") + + time.sleep(0.1) + + def targets(self): + """Run `targets` command.""" + result = self.command("targets").decode() + # TargetName Type Endian TapName State + # -- ------------------ ---------- ------ ------------------ -------- + # 0* riscv.cpu riscv little riscv.cpu halted + lines = result.splitlines() + headers = lines[0].split() + data = [] + for line in lines[2:]: + if line.strip(): + data.append(dict(zip(headers, line.split()[1:]))) + return data + + def wait_until_running(self, harts): + """Wait until the given harts are running.""" + start = time.time() + while True: + targets = self.targets() + if all(targets[hart.id]["State"] == "running" for hart in harts): + return + if time.time() - start > self.timeout: + raise TestLibError("Timed out waiting for targets to run.") + + def set_available(self, harts): + """Set the given harts to available, and any others to be unavailable. + This uses a custom DMI register (0x1f) that is only implemented in + spike.""" + available_mask = 0 + for hart in harts: + available_mask |= 1 << hart.id + self.command(f"riscv dmi_write 0x1f 0x{available_mask:x}") + + # Wait until it happened. + start = time.time() + while True: + currently_available = set() + currently_unavailable = set() + for i, target in enumerate(self.targets()): + if target["State"] == "unavailable": + currently_unavailable.add(i) + else: + currently_available.add(i) + if currently_available == set(hart.id for hart in harts): + return + if time.time() - start > self.timeout: + raise TestLibError("Timed out waiting for hart availability.") + class OpenocdCli: def __init__(self, port=4444): self.child = pexpect.spawn( @@ -493,6 +589,9 @@ class UnknownThread(Exception): def __init__(self, explanation): Exception.__init__(self, explanation) +class ThreadTerminated(Exception): + pass + Thread = collections.namedtuple('Thread', ('id', 'description', 'target_id', 'name', 'frame')) @@ -590,6 +689,15 @@ def parse_rhs(text): raise TestLibError(f"Unexpected input: {tokens!r}") return result +class CommandException(Exception): + pass + +class CommandSendTimeout(CommandException): + pass + +class CommandCompleteTimeout(CommandException): + pass + class Gdb: """A single gdb class which can interact with one or more gdb instances.""" @@ -600,7 +708,8 @@ class Gdb: 11, 149, 107, 163, 73, 47, 43, 173, 7, 109, 101, 103, 191, 2, 139, 97, 193, 157, 3, 29, 79, 113, 5, 89, 19, 37, 71, 179, 59, 137, 53) - def __init__(self, target, ports, cmd=None, timeout=60, binaries=None): + def __init__(self, target, ports, cmd=None, timeout=60, binaries=None, + logremote=False): assert ports self.target = target @@ -635,7 +744,16 @@ class Gdb: # Force consistency. self.command("set print entry-values no", reset_delays=None) self.command(f"set remotetimeout {self.timeout}", reset_delays=None) - self.command(f"set remotetimeout {self.target.timeout_sec}") + if logremote: + # pylint: disable-next=consider-using-with + remotelog = tempfile.NamedTemporaryFile( + prefix=f"remote.gdb@{port}-", suffix=".log") + if print_log_names: + real_stdout.write( + f"Temporary remotelog: {remotelog.name}\n") + self.logfiles.append(remotelog) + self.command(f"set remotelogfile {remotelog.name}", + reset_delays=None) self.active_child = self.children[0] def connect(self): @@ -691,6 +809,8 @@ class Gdb: output = self.command(f"thread {h['thread'].id}", ops=5) if "Unknown" in output: raise UnknownThread(output) + if f"Thread ID {h['thread'].id} has terminated" in output: + raise ThreadTerminated(output) def push_state(self): self.stack.append({ @@ -718,8 +838,15 @@ class Gdb: reset_delays=None) timeout = max(1, ops) * self.timeout self.active_child.sendline(command) - self.active_child.expect("\n", timeout=timeout) - self.active_child.expect(r"\(gdb\)", timeout=timeout) + try: + self.active_child.expect(re.escape(command), timeout=timeout) + self.active_child.expect("\n", timeout=timeout) + except pexpect.exceptions.TIMEOUT as exc: + raise CommandSendTimeout(command) from exc + try: + self.active_child.expect(r"\(gdb\)", timeout=timeout) + except pexpect.exceptions.TIMEOUT as exc: + raise CommandCompleteTimeout(command) from exc output = self.active_child.before.decode("utf-8", errors="ignore") ansi_escape = re.compile(r'\x1B(?:[@-Z\\-_]|\[[0-?]*[ -/]*[@-~])') return ansi_escape.sub('', output).strip() @@ -814,9 +941,10 @@ class Gdb: return self.active_child.before.strip().decode() def interrupt_all(self): - for child in self.children: - self.select_child(child) - self.interrupt() + with PrivateState(self): + for child in self.children: + self.select_child(child) + self.interrupt() def x(self, address, size='w', count=1): output = self.command(f"x/{count}{size} {address}", ops=count / 16) @@ -948,12 +1076,16 @@ class PrivateState: def load_excluded_tests(excluded_tests_file, target_name): result = [] - if excluded_tests_file is None or len(excluded_tests_file) == 0: + if excluded_tests_file is None: + # No list of excluded tests was specified return result target_excludes = {} with open(excluded_tests_file, encoding="utf-8") as file: raw_data = yaml.safe_load(file) + if raw_data is None: + # File contains no targets + return result for (target, test_list) in raw_data.items(): if not isinstance(test_list, list): raise ValueError( @@ -976,11 +1108,15 @@ def load_excluded_tests(excluded_tests_file, target_name): def run_all_tests(module, target, parsed): todo = [] + if not parsed.hart is None: + target_hart = target.harts[parsed.hart] + else: + target_hart = None for name in dir(module): definition = getattr(module, name) if isinstance(definition, type) and hasattr(definition, 'test') and \ (not parsed.test or any(test in name for test in parsed.test)): - todo.append((name, definition, None)) + todo.append((name, definition, target_hart)) if parsed.list_tests: for name, definition, hart in todo: @@ -1002,6 +1138,8 @@ def run_all_tests(module, target, parsed): gcc_cmd = parsed.gcc global target_timeout # pylint: disable=global-statement target_timeout = parsed.target_timeout + global remotelogfile_enable # pylint: disable=global-statement + remotelogfile_enable = parsed.remotelogfile_enable examine_added = False for hart in target.harts: @@ -1048,7 +1186,10 @@ def run_tests(parsed, target, todo): result = instance.run() log_fd.write(f"Result: {result}\n") log_fd.write(f"Logfile: {log_name}\n") - log_fd.write(f"Reproduce: {sys.argv[0]} {parsed.target} {name}\n") + log_fd.write(f"Reproduce: {sys.argv[0]} {parsed.target} {name}") + if len(target.harts) > 1: + log_fd.write(f" --hart {instance.hart.id}") + log_fd.write("\n") finally: sys.stdout = real_stdout log_fd.write(f"Time elapsed: {time.time() - start:.2f}s\n") @@ -1107,6 +1248,16 @@ def add_test_run_options(parser): help="Specify yaml file listing tests to exclude") parser.add_argument("--target-timeout", help="Override the base target timeout.", default=None, type=int) + parser.add_argument("--seed", + help="Use user-specified seed value for PRNG.", default=None, + type=int) + parser.add_argument("--remotelogfile-enable", + help="If specified save GDB will record remote session to a file", + action="store_true", + default=False) + parser.add_argument("--hart", + help="Run tests against this hart in multihart tests.", + default=None, type=int) def header(title, dash='-', length=78): if title: @@ -1133,10 +1284,12 @@ class BaseTest: def __init__(self, target, hart=None): self.target = target - if hart: + if not hart is None: self.hart = hart else: + import random # pylint: disable=import-outside-toplevel self.hart = random.choice(target.harts) + #self.hart = target.harts[-1] self.server = None self.target_process = None self.binary = None @@ -1250,6 +1403,7 @@ class BaseTest: gdb_cmd = None target_timeout = None +remotelogfile_enable = False class GdbTest(BaseTest): def __init__(self, target, hart=None): BaseTest.__init__(self, target, hart=hart) @@ -1266,7 +1420,8 @@ class GdbTest(BaseTest): self.gdb = Gdb(self.target, self.server.gdb_ports, cmd=gdb_cmd, timeout=target_timeout or self.target.timeout_sec, - binaries=self.binaries) + binaries=self.binaries, + logremote=remotelogfile_enable) self.logs += self.gdb.lognames() self.gdb.connect() @@ -1308,6 +1463,7 @@ class GdbTest(BaseTest): self.gdb.p(f"$pc={symbol}") self.gdb.select_hart(self.hart) + self.gdb.command(f"monitor targets {self.hart.id}") def disable_pmp(self): # Disable physical memory protection by allowing U mode access to all @@ -1326,6 +1482,13 @@ class GdbTest(BaseTest): # PMP registers are optional pass + def disable_timer(self, interrupt=False): + for hart in self.target.harts: + self.gdb.select_hart(hart) + if interrupt: + self.gdb.interrupt() + self.gdb.p("$mie=$mie & ~0x80") + def exit(self, expected_result=10): self.gdb.command("delete") self.gdb.b("_exit") diff --git a/isa/Makefile b/isa/Makefile index d66b901..bf85e1f 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -14,6 +14,10 @@ include $(src_dir)/rv64ua/Makefrag include $(src_dir)/rv64uf/Makefrag include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64uzfh/Makefrag +include $(src_dir)/rv64uzba/Makefrag +include $(src_dir)/rv64uzbb/Makefrag +include $(src_dir)/rv64uzbc/Makefrag +include $(src_dir)/rv64uzbs/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64ssvnapot/Makefrag include $(src_dir)/rv64mi/Makefrag @@ -26,6 +30,10 @@ include $(src_dir)/rv32ua/Makefrag include $(src_dir)/rv32uf/Makefrag include $(src_dir)/rv32ud/Makefrag include $(src_dir)/rv32uzfh/Makefrag +include $(src_dir)/rv32uzba/Makefrag +include $(src_dir)/rv32uzbb/Makefrag +include $(src_dir)/rv32uzbc/Makefrag +include $(src_dir)/rv32uzbs/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -50,10 +58,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ define compile_template @@ -86,6 +94,10 @@ $(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) +$(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbc,-march=rv32g_zbc -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbs,-march=rv32g_zbs -mabi=ilp32)) $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) ifeq ($(XLEN),64) @@ -96,6 +108,10 @@ $(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) +$(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) +$(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64)) +$(eval $(call compile_template,rv64uzbc,-march=rv64g_zbc -mabi=lp64)) +$(eval $(call compile_template,rv64uzbs,-march=rv64g_zbs -mabi=lp64)) $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) diff --git a/isa/rv32uzba/Makefrag b/isa/rv32uzba/Makefrag new file mode 100644 index 0000000..39a2c99 --- /dev/null +++ b/isa/rv32uzba/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv32uzba tests +#----------------------------------------------------------------------- + +rv32uzba_sc_tests = \ + sh1add \ + sh2add \ + sh3add \ + +rv32uzba_p_tests = $(addprefix rv32uzba-p-, $(rv32uzba_sc_tests)) +rv32uzba_v_tests = $(addprefix rv32uzba-v-, $(rv32uzba_sc_tests)) +rv32uzba_ps_tests = $(addprefix rv32uzba-ps-, $(rv32uzba_sc_tests)) + +spike_tests += $(rv32uzba_p_tests) $(rv32uzba_v_tests) diff --git a/isa/rv32uzba/sh1add.S b/isa/rv32uzba/sh1add.S new file mode 100644 index 0000000..03ae190 --- /dev/null +++ b/isa/rv32uzba/sh1add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh1add.S +#----------------------------------------------------------------------------- +# +# Test sh1add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh1add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh1add, 0x00000003, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh1add, 0x0000000d, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh1add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh1add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh1add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh1add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh1add, 0xfffffffe, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh1add, 0x00007ffd, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh1add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh1add, 0xffff7ffe, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh1add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh1add, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh1add, 0xfffffffd, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh1add, 0x80000001, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 ); + TEST_RR_ZEROSRC12( 37, sh1add, 0 ); + TEST_RR_ZERODEST( 38, sh1add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzba/sh2add.S b/isa/rv32uzba/sh2add.S new file mode 100644 index 0000000..057dba5 --- /dev/null +++ b/isa/rv32uzba/sh2add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh2add.S +#----------------------------------------------------------------------------- +# +# Test sh2add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh2add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh2add, 0x00000005, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh2add, 0x00000013, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh2add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh2add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh2add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh2add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh2add, 0xfffffffc, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh2add, 0x00007ffb, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh2add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh2add, 0xffff7ffc, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh2add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh2add, 0xfffffffd, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh2add, 0xfffffffb, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh2add, 0x80000003, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 ); + TEST_RR_ZEROSRC12( 37, sh2add, 0 ); + TEST_RR_ZERODEST( 38, sh2add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzba/sh3add.S b/isa/rv32uzba/sh3add.S new file mode 100644 index 0000000..530241e --- /dev/null +++ b/isa/rv32uzba/sh3add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh3add.S +#----------------------------------------------------------------------------- +# +# Test sh3add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh3add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh3add, 0x00000009, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh3add, 0x0000001f, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh3add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh3add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh3add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh3add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh3add, 0xfffffff8, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh3add, 0x00007ff7, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh3add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh3add, 0xffff7ff8, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh3add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh3add, 0xfffffff9, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh3add, 0xfffffff7, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh3add, 0x80000007, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 ); + TEST_RR_ZEROSRC12( 37, sh3add, 0 ); + TEST_RR_ZERODEST( 38, sh3add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/Makefrag b/isa/rv32uzbb/Makefrag new file mode 100644 index 0000000..752f8d0 --- /dev/null +++ b/isa/rv32uzbb/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv32uzbb tests +#----------------------------------------------------------------------- + +rv32uzbb_sc_tests = \ + andn \ + clz \ + cpop \ + ctz \ + max maxu \ + min minu \ + orc_b \ + orn \ + rev8 \ + rol \ + ror \ + rori \ + sext_b sext_h \ + xnor \ + zext_h \ + +rv32uzbb_p_tests = $(addprefix rv32uzbb-p-, $(rv32uzbb_sc_tests)) +rv32uzbb_v_tests = $(addprefix rv32uzbb-v-, $(rv32uzbb_sc_tests)) +rv32uzbb_ps_tests = $(addprefix rv32uzbb-ps-, $(rv32uzbb_sc_tests)) + +spike_tests += $(rv32uzbb_p_tests) $(rv32uzbb_v_tests) diff --git a/isa/rv32uzbb/andn.S b/isa/rv32uzbb/andn.S new file mode 100644 index 0000000..f54aa1a --- /dev/null +++ b/isa/rv32uzbb/andn.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/andn.S" diff --git a/isa/rv32uzbb/clz.S b/isa/rv32uzbb/clz.S new file mode 100644 index 0000000..4b349ad --- /dev/null +++ b/isa/rv32uzbb/clz.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clz.S +#----------------------------------------------------------------------------- +# +# Test clz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clz, 32, 0x00000000); + TEST_R_OP( 3, clz, 31, 0x00000001); + TEST_R_OP( 4, clz, 30, 0x00000003); + + TEST_R_OP( 5, clz, 0, 0xffff8000 ); + TEST_R_OP( 6, clz, 8, 0x00800000 ); + TEST_R_OP( 7, clz, 0, 0xffff8000 ); + + TEST_R_OP( 8, clz, 17, 0x00007fff); + TEST_R_OP( 9, clz, 1, 0x7fffffff); + TEST_R_OP( 10, clz, 13, 0x0007ffff ); + + TEST_R_OP( 11, clz, 0, 0x80000000); + TEST_R_OP( 12, clz, 3, 0x121f5000); + + TEST_R_OP( 13, clz, 5, 0x04000000); + TEST_R_OP( 14, clz, 28, 0x0000000e); + TEST_R_OP( 15, clz, 2, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clz, 28, 13); + TEST_R_SRC1_EQ_DEST( 17, clz, 28, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clz, 28, 13); + TEST_R_DEST_BYPASS( 29, 1, clz, 27, 19); + TEST_R_DEST_BYPASS( 20, 2, clz, 26, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + + TEST_R_OP( 21, clz, 5, 0x070f8000 ); + TEST_R_OP( 22, clz, 4, 0x08008000 ); + TEST_R_OP( 23, clz, 3, 0x18008000 ); + + TEST_R_OP( 24, clz, 17, 0x00007fff); + TEST_R_OP( 25, clz, 1, 0x7fffffff); + TEST_R_OP( 26, clz, 13, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/cpop.S b/isa/rv32uzbb/cpop.S new file mode 100644 index 0000000..4d97758 --- /dev/null +++ b/isa/rv32uzbb/cpop.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpop.S +#----------------------------------------------------------------------------- +# +# Test cpop instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpop, 0, 0x00000000); + TEST_R_OP( 3, cpop, 1, 0x00000001); + TEST_R_OP( 4, cpop, 2, 0x00000003); + + TEST_R_OP( 5, cpop, 17, 0xffff8000 ); + TEST_R_OP( 6, cpop, 1, 0x00800000 ); + TEST_R_OP( 7, cpop, 18, 0xffff6000 ); + + TEST_R_OP( 8, cpop, 15, 0x00007fff); + TEST_R_OP( 9, cpop, 31, 0x7fffffff); + TEST_R_OP( 10, cpop, 19, 0x0007ffff ); + + TEST_R_OP( 11, cpop, 1, 0x80000000); + TEST_R_OP( 12, cpop, 9, 0x121f5000); + + TEST_R_OP( 13, cpop, 0, 0x00000000); + TEST_R_OP( 14, cpop, 3, 0x0000000e); + TEST_R_OP( 15, cpop, 7, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpop, 8, 0x007f8000 ); + TEST_R_OP( 22, cpop, 2, 0x00808000 ); + TEST_R_OP( 23, cpop, 3, 0x01808000 ); + + TEST_R_OP( 24, cpop, 17, 0x30007fff); + TEST_R_OP( 25, cpop, 30, 0x77ffffff); + TEST_R_OP( 26, cpop, 19, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/ctz.S b/isa/rv32uzbb/ctz.S new file mode 100644 index 0000000..58bf2f1 --- /dev/null +++ b/isa/rv32uzbb/ctz.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctz.S +#----------------------------------------------------------------------------- +# +# Test ctz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctz, 32, 0x00000000); + TEST_R_OP( 3, ctz, 0, 0x00000001); + TEST_R_OP( 4, ctz, 0, 0x00000003); + + TEST_R_OP( 5, ctz, 15, 0xffff8000 ); + TEST_R_OP( 6, ctz, 23, 0x00800000 ); + TEST_R_OP( 7, ctz, 15, 0xffff8000 ); + + TEST_R_OP( 8, ctz, 0, 0x00007fff); + TEST_R_OP( 9, ctz, 0, 0x7fffffff); + TEST_R_OP( 10, ctz, 0, 0x0007ffff ); + + TEST_R_OP( 11, ctz, 31, 0x80000000); + TEST_R_OP( 12, ctz, 12, 0x121f5000); + + TEST_R_OP( 13, ctz, 30, 0xc0000000); + TEST_R_OP( 14, ctz, 1, 0x0000000e); + TEST_R_OP( 15, ctz, 0, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctz, 15, 0x007f8000 ); + TEST_R_OP( 22, ctz, 15, 0x00808000 ); + TEST_R_OP( 23, ctz, 12, 0x01809000 ); + + TEST_R_OP( 24, ctz, 0, 0x00007fff); + TEST_R_OP( 25, ctz, 0, 0x7fffffff); + TEST_R_OP( 26, ctz, 0, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/max.S b/isa/rv32uzbb/max.S new file mode 100644 index 0000000..ecd713c --- /dev/null +++ b/isa/rv32uzbb/max.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/max.S" diff --git a/isa/rv32uzbb/maxu.S b/isa/rv32uzbb/maxu.S new file mode 100644 index 0000000..27cfc29 --- /dev/null +++ b/isa/rv32uzbb/maxu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/maxu.S" diff --git a/isa/rv32uzbb/min.S b/isa/rv32uzbb/min.S new file mode 100644 index 0000000..c24a514 --- /dev/null +++ b/isa/rv32uzbb/min.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/min.S" diff --git a/isa/rv32uzbb/minu.S b/isa/rv32uzbb/minu.S new file mode 100644 index 0000000..4b2549d --- /dev/null +++ b/isa/rv32uzbb/minu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/minu.S" diff --git a/isa/rv32uzbb/orc_b.S b/isa/rv32uzbb/orc_b.S new file mode 100644 index 0000000..7fb8441 --- /dev/null +++ b/isa/rv32uzbb/orc_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orc.b.S +#----------------------------------------------------------------------------- +# +# Test orc.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 3, orc.b, 0x000000ff, 0x00000001); + TEST_R_OP( 4, orc.b, 0x000000ff, 0x00000003); + + TEST_R_OP( 5, orc.b, 0xffffff00, 0xffff8000 ); + TEST_R_OP( 6, orc.b, 0x00ff0000, 0x00800000 ); + TEST_R_OP( 7, orc.b, 0xffffff00, 0xffff8000 ); + + TEST_R_OP( 8, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 9, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 10, orc.b, 0x00ffffff, 0x0007ffff ); + + TEST_R_OP( 11, orc.b, 0xff000000, 0x80000000); + TEST_R_OP( 12, orc.b, 0xffffff00, 0x121f5000); + + TEST_R_OP( 13, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 14, orc.b, 0x000000ff, 0x0000000e); + TEST_R_OP( 15, orc.b, 0xffffffff, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13); + TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13); + TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19); + TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, orc.b, 0x00ffff00, 0x007f8000 ); + TEST_R_OP( 22, orc.b, 0x00ffff00, 0x00808000 ); + TEST_R_OP( 23, orc.b, 0xffffff00, 0x01808000 ); + + TEST_R_OP( 24, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 25, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 26, orc.b, 0x00ffffff, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/orn.S b/isa/rv32uzbb/orn.S new file mode 100644 index 0000000..cdfafcc --- /dev/null +++ b/isa/rv32uzbb/orn.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/orn.S" diff --git a/isa/rv32uzbb/rev8.S b/isa/rv32uzbb/rev8.S new file mode 100644 index 0000000..2828f27 --- /dev/null +++ b/isa/rv32uzbb/rev8.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rev8.S +#----------------------------------------------------------------------------- +# +# Test rev8 instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, rev8, 0x00000000, 0x00000000); + TEST_R_OP( 3, rev8, 0x01000000, 0x00000001); + TEST_R_OP( 4, rev8, 0x03000000, 0x00000003); + + TEST_R_OP( 5, rev8, 0x0080ffff, 0xffff8000 ); + TEST_R_OP( 6, rev8, 0x00008000, 0x00800000 ); + TEST_R_OP( 7, rev8, 0x0080ffff, 0xffff8000 ); + + TEST_R_OP( 8, rev8, 0xff7f0000, 0x00007fff); + TEST_R_OP( 9, rev8, 0xffffff7f, 0x7fffffff); + TEST_R_OP( 10, rev8, 0xffff0700, 0x0007ffff ); + + TEST_R_OP( 11, rev8, 0x00000080, 0x80000000); + TEST_R_OP( 12, rev8, 0x00501f12, 0x121f5000); + + TEST_R_OP( 13, rev8, 0x00000000, 0x00000000); + TEST_R_OP( 14, rev8, 0x0e000000, 0x0000000e); + TEST_R_OP( 15, rev8, 0x41134020, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d000000, 13); + TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b000000, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d000000, 13); + TEST_R_DEST_BYPASS( 29, 1, rev8, 0x13000000, 19); + TEST_R_DEST_BYPASS( 20, 2, rev8, 0x22000000, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, rev8, 0x00807f00, 0x007f8000 ); + TEST_R_OP( 22, rev8, 0x00808000, 0x00808000 ); + TEST_R_OP( 23, rev8, 0x00808001, 0x01808000 ); + + TEST_R_OP( 24, rev8, 0xff7f0000, 0x00007fff); + TEST_R_OP( 25, rev8, 0xffffff7f, 0x7fffffff); + TEST_R_OP( 26, rev8, 0xffff0700, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/rol.S b/isa/rv32uzbb/rol.S new file mode 100644 index 0000000..a7c04fe --- /dev/null +++ b/isa/rv32uzbb/rol.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rol.S +#----------------------------------------------------------------------------- +# +# Test rol instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rol, 0x00000001, 0x00000001, 0 ); + TEST_RR_OP( 3, rol, 0x00000002, 0x00000001, 1 ); + TEST_RR_OP( 4, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_OP( 5, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_OP( 6, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_OP( 7, rol, 0xffffffff, 0xffffffff, 0 ); + TEST_RR_OP( 8, rol, 0xffffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, rol, 0xffffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, rol, 0xffffffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, rol, 0xffffffff, 0xffffffff, 31 ); + + TEST_RR_OP( 12, rol, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, rol, 0x42424242, 0x21212121, 1 ); + TEST_RR_OP( 14, rol, 0x90909090, 0x21212121, 7 ); + TEST_RR_OP( 15, rol, 0x48484848, 0x21212121, 14 ); + TEST_RR_OP( 16, rol, 0x90909090, 0x21212121, 31 ); + + # Verify that rotates only use bottom five bits + + TEST_RR_OP( 17, rol, 0x21212121, 0x21212121, 0xffffffe0 ); + TEST_RR_OP( 18, rol, 0x42424242, 0x21212121, 0xffffffe1 ); + TEST_RR_OP( 19, rol, 0x90909090, 0x21212121, 0xffffffe7 ); + TEST_RR_OP( 20, rol, 0x48484848, 0x21212121, 0xffffffee ); + TEST_RR_OP( 21, rol, 0x90909090, 0x21212121, 0xffffffff ); + + # Verify that rotates ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, rol, 0x12345678, 0x12345678, 0 ); + TEST_RR_OP( 45, rol, 0x23456781, 0x12345678, 4 ); + TEST_RR_OP( 46, rol, 0x92345678, 0x92345678, 0 ); + TEST_RR_OP( 47, rol, 0x93456789, 0x99345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x80000000, 0x00000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x80000000, 0x00000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rol, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rol, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rol, 0 ); + TEST_RR_ZERODEST( 43, rol, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/ror.S b/isa/rv32uzbb/ror.S new file mode 100644 index 0000000..5b57740 --- /dev/null +++ b/isa/rv32uzbb/ror.S @@ -0,0 +1,91 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test ror instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, ror, 0x00000001, 0x00000001, 0 ); + TEST_RR_OP( 3, ror, 0x80000000, 0x00000001, 1 ); + TEST_RR_OP( 4, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_OP( 5, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_OP( 6, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_OP( 7, ror, 0xffffffff, 0xffffffff, 0 ); + TEST_RR_OP( 8, ror, 0xffffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, ror, 0xffffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, ror, 0xffffffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, ror, 0xffffffff, 0xffffffff, 31 ); + + TEST_RR_OP( 12, ror, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, ror, 0x90909090, 0x21212121, 1 ); + TEST_RR_OP( 14, ror, 0x42424242, 0x21212121, 7 ); + TEST_RR_OP( 15, ror, 0x84848484, 0x21212121, 14 ); + TEST_RR_OP( 16, ror, 0x42424242, 0x21212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, ror, 0x21212121, 0x21212121, 0xffffffc0 ); + TEST_RR_OP( 18, ror, 0x90909090, 0x21212121, 0xffffffc1 ); + TEST_RR_OP( 19, ror, 0x42424242, 0x21212121, 0xffffffc7 ); + TEST_RR_OP( 20, ror, 0x84848484, 0x21212121, 0xffffffce ); + + TEST_RR_OP( 21, ror, 0x42424242, 0x21212121, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, ror, 0x60000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x00000002, 0x00000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x00000002, 0x00000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_ZEROSRC1( 40, ror, 0, 15 ); + TEST_RR_ZEROSRC2( 41, ror, 32, 32 ); + TEST_RR_ZEROSRC12( 42, ror, 0 ); + TEST_RR_ZERODEST( 43, ror, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/rori.S b/isa/rv32uzbb/rori.S new file mode 100644 index 0000000..c98ed85 --- /dev/null +++ b/isa/rv32uzbb/rori.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, rori, 0x00000001, 0x00000001, 0 ); + TEST_IMM_OP( 3, rori, 0x80000000, 0x00000001, 1 ); + TEST_IMM_OP( 4, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_OP( 5, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_OP( 6, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_OP( 7, rori, 0xffffffff, 0xffffffff, 0 ); + TEST_IMM_OP( 8, rori, 0xffffffff, 0xffffffff, 1 ); + TEST_IMM_OP( 9, rori, 0xffffffff, 0xffffffff, 7 ); + TEST_IMM_OP( 10, rori, 0xffffffff, 0xffffffff, 14 ); + TEST_IMM_OP( 11, rori, 0xffffffff, 0xffffffff, 31 ); + + TEST_IMM_OP( 12, rori, 0x21212121, 0x21212121, 0 ); + TEST_IMM_OP( 13, rori, 0x90909090, 0x21212121, 1 ); + TEST_IMM_OP( 14, rori, 0x42424242, 0x21212121, 7 ); + TEST_IMM_OP( 15, rori, 0x84848484, 0x21212121, 14 ); + TEST_IMM_OP( 16, rori, 0x42424242, 0x21212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x02000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, rori, 0, 31 ); + TEST_IMM_ZERODEST( 28, rori, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/sext_b.S b/isa/rv32uzbb/sext_b.S new file mode 100644 index 0000000..f73e107 --- /dev/null +++ b/isa/rv32uzbb/sext_b.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/sext_b.S" diff --git a/isa/rv32uzbb/sext_h.S b/isa/rv32uzbb/sext_h.S new file mode 100644 index 0000000..d4b4206 --- /dev/null +++ b/isa/rv32uzbb/sext_h.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/sext_h.S" diff --git a/isa/rv32uzbb/xnor.S b/isa/rv32uzbb/xnor.S new file mode 100644 index 0000000..c5e453a --- /dev/null +++ b/isa/rv32uzbb/xnor.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/xnor.S" diff --git a/isa/rv32uzbb/zext_h.S b/isa/rv32uzbb/zext_h.S new file mode 100644 index 0000000..d339ccc --- /dev/null +++ b/isa/rv32uzbb/zext_h.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/zext_h.S" diff --git a/isa/rv32uzbc/Makefrag b/isa/rv32uzbc/Makefrag new file mode 100644 index 0000000..7dcf6d5 --- /dev/null +++ b/isa/rv32uzbc/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv32uzbc tests +#----------------------------------------------------------------------- + +rv32uzbc_sc_tests = \ + clmul \ + clmulh \ + clmulr \ + +rv32uzbc_p_tests = $(addprefix rv32uzbc-p-, $(rv32uzbc_sc_tests)) +rv32uzbc_v_tests = $(addprefix rv32uzbc-v-, $(rv32uzbc_sc_tests)) +rv32uzbc_ps_tests = $(addprefix rv32uzbc-ps-, $(rv32uzbc_sc_tests)) + +spike_tests += $(rv32uzbc_p_tests) $(rv32uzbc_v_tests) diff --git a/isa/rv32uzbc/clmul.S b/isa/rv32uzbc/clmul.S new file mode 100644 index 0000000..8a50300 --- /dev/null +++ b/isa/rv32uzbc/clmul.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmul.S +#----------------------------------------------------------------------------- +# +# Test clmul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmul, 0x00005a00, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, clmul, 0x00005b40, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, clmul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmul, 0x00000009, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmul, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, clmul, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, clmul, 0x00000000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, clmul, 0xfffc324f, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, clmul, 0xfffc324f, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, clmul, 0x00000000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, clmul, 0x55555555, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, clmul, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, clmul, 0xffffffff, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmul, 0x51, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmul, 0x62, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmul, 0 ); + TEST_RR_ZERODEST( 29, clmul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbc/clmulh.S b/isa/rv32uzbc/clmulh.S new file mode 100644 index 0000000..b5fde88 --- /dev/null +++ b/isa/rv32uzbc/clmulh.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulh.S +#----------------------------------------------------------------------------- +# +# Test clmulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulh, 0x00003600, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, clmulh, 0x000036c0, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, clmulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulh, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, clmulh, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulh, 0x7fffc000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, clmulh, 0x000133cd, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, clmulh, 0x000133cd, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, clmulh, 0x55550000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, clmulh, 0x55555555, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, clmulh, 0x00000000, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, clmulh, 0x00000000, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulh, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulh, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulh, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulh, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulh, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulh, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulh, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulh, 0 ); + TEST_RR_ZERODEST( 29, clmulh, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbc/clmulr.S b/isa/rv32uzbc/clmulr.S new file mode 100644 index 0000000..dc255ec --- /dev/null +++ b/isa/rv32uzbc/clmulr.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulr.S +#----------------------------------------------------------------------------- +# +# Test clmulr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulr, 0x00006c00, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, clmulr, 0x00006d80, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, clmulr, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulr, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulr, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulr, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, clmulr, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulr, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, clmulr, 0x0002679b, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, clmulr, 0x0002679b, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, clmulr, 0xaaaa0000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, clmulr, 0xaaaaaaaa, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, clmulr, 0x00000001, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, clmulr, 0x00000001, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulr, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulr, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulr, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulr, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulr, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulr, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulr, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulr, 0 ); + TEST_RR_ZERODEST( 29, clmulr, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbs/Makefrag b/isa/rv32uzbs/Makefrag new file mode 100644 index 0000000..7af7c42 --- /dev/null +++ b/isa/rv32uzbs/Makefrag @@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv32uzbs tests +#----------------------------------------------------------------------- + +rv32uzbs_sc_tests = \ + bclr bclri \ + bext bexti \ + binv binvi \ + bset bseti \ + +rv32uzbs_p_tests = $(addprefix rv32uzbs-p-, $(rv32uzbs_sc_tests)) +rv32uzbs_v_tests = $(addprefix rv32uzbs-v-, $(rv32uzbs_sc_tests)) +rv32uzbs_ps_tests = $(addprefix rv32uzbs-ps-, $(rv32uzbs_sc_tests)) + +spike_tests += $(rv32uzbs_p_tests) $(rv32uzbs_v_tests) diff --git a/isa/rv32uzbs/bclr.S b/isa/rv32uzbs/bclr.S new file mode 100644 index 0000000..10f7e50 --- /dev/null +++ b/isa/rv32uzbs/bclr.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bclr.S" diff --git a/isa/rv32uzbs/bclri.S b/isa/rv32uzbs/bclri.S new file mode 100644 index 0000000..2f709d8 --- /dev/null +++ b/isa/rv32uzbs/bclri.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bclri.S" diff --git a/isa/rv32uzbs/bext.S b/isa/rv32uzbs/bext.S new file mode 100644 index 0000000..0f838e5 --- /dev/null +++ b/isa/rv32uzbs/bext.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bext.S" diff --git a/isa/rv32uzbs/bexti.S b/isa/rv32uzbs/bexti.S new file mode 100644 index 0000000..91ee2d6 --- /dev/null +++ b/isa/rv32uzbs/bexti.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bexti.S" diff --git a/isa/rv32uzbs/binv.S b/isa/rv32uzbs/binv.S new file mode 100644 index 0000000..55ea39b --- /dev/null +++ b/isa/rv32uzbs/binv.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/binv.S" diff --git a/isa/rv32uzbs/binvi.S b/isa/rv32uzbs/binvi.S new file mode 100644 index 0000000..5874363 --- /dev/null +++ b/isa/rv32uzbs/binvi.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/binvi.S" diff --git a/isa/rv32uzbs/bset.S b/isa/rv32uzbs/bset.S new file mode 100644 index 0000000..4220823 --- /dev/null +++ b/isa/rv32uzbs/bset.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bset.S" diff --git a/isa/rv32uzbs/bseti.S b/isa/rv32uzbs/bseti.S new file mode 100644 index 0000000..4a6179e --- /dev/null +++ b/isa/rv32uzbs/bseti.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bseti.S" diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 1223f71..153963a 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -26,6 +26,9 @@ RVTEST_CODE_BEGIN 1: csrw mtvec, a0 + # Enable interrupts; see https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214 + csrsi mstatus, MSTATUS_MIE + # Skip tselect if hard-wired. csrw tselect, x0 csrr a1, tselect diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index f02a1af..8579c01 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -20,6 +20,7 @@ RVTEST_CODE_BEGIN # indicate it's a load test li s1, CAUSE_MISALIGNED_LOAD + li s2, CAUSE_LOAD_ACCESS #define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1))) @@ -56,6 +57,7 @@ RVTEST_CODE_BEGIN # indicate it's a store test li s1, CAUSE_MISALIGNED_STORE + li s2, CAUSE_STORE_ACCESS /* Check that a misaligned store has some effect and takes no exception, or takes no effect and generates an exception. This is not very @@ -96,7 +98,10 @@ RVTEST_CODE_BEGIN .global mtvec_handler mtvec_handler: csrr t0, mcause - bne t0, s1, fail + beq t0, s1, 1f + beq t0, s2, 1f + j fail +1: csrr t0, mbadaddr beqz t0, 1f diff --git a/isa/rv64ssvnapot/napot.S b/isa/rv64ssvnapot/napot.S index 92d2b49..fbc4014 100644 --- a/isa/rv64ssvnapot/napot.S +++ b/isa/rv64ssvnapot/napot.S @@ -121,6 +121,7 @@ RVTEST_CODE_BEGIN # Do a store to MY_VA li a0, MY_VA li a1, 42 +napot_store: sw a1, (a0) # Clear MPRV @@ -153,6 +154,16 @@ RVTEST_CODE_BEGIN .align 2 .global mtvec_handler mtvec_handler: + # Skip if Svnapot is not implemented. + csrr t5, mcause + li t6, CAUSE_STORE_PAGE_FAULT + bne t5, t6, die + csrr t5, mepc + la t6, napot_store + bne t5, t6, die + csrr t5, mtval + li t6, MY_VA + beq t5, t6, pass die: RVTEST_FAIL diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S index ab0d025..39fb156 100644 --- a/isa/rv64ua/lrsc.S +++ b/isa/rv64ua/lrsc.S @@ -62,7 +62,7 @@ addi a2, a2, 1 add a4, a4, a2 sc.w a4, a4, (a0) bnez a4, 1b -add a1, a1, -1 +addi a1, a1, -1 bnez a1, 1b # wait for all cores to finish diff --git a/isa/rv64uzba/Makefrag b/isa/rv64uzba/Makefrag new file mode 100644 index 0000000..a2428f3 --- /dev/null +++ b/isa/rv64uzba/Makefrag @@ -0,0 +1,16 @@ +#======================================================================= +# Makefrag for rv64uzba tests +#----------------------------------------------------------------------- + +rv64uzba_sc_tests = \ + add_uw \ + sh1add sh1add_uw \ + sh2add sh2add_uw \ + sh3add sh3add_uw \ + slli_uw \ + +rv64uzba_p_tests = $(addprefix rv64uzba-p-, $(rv64uzba_sc_tests)) +rv64uzba_v_tests = $(addprefix rv64uzba-v-, $(rv64uzba_sc_tests)) +rv64uzba_ps_tests = $(addprefix rv64uzba-ps-, $(rv64uzba_sc_tests)) + +spike_tests += $(rv64uzba_p_tests) $(rv64uzba_v_tests) diff --git a/isa/rv64uzba/add_uw.S b/isa/rv64uzba/add_uw.S new file mode 100644 index 0000000..cd89628 --- /dev/null +++ b/isa/rv64uzba/add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# add_uw.S +#----------------------------------------------------------------------------- +# +# Test add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, add.uw, 0x00000002, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, add.uw, 0x0000000a, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, add.uw, 0x0000000080000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, add.uw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, add.uw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, add.uw, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, add.uw, 0x0000000080007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, add.uw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, add.uw, 0x0000000100000000, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, add.uw, 0x00000000fffffffe, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, add.uw, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, add.uw, 24, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, add.uw, 25, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, add.uw, 26, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, add.uw, 24, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, add.uw, 25, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, add.uw, 26, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, add.uw, 26, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, add.uw, 26, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, add.uw, 26, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, add.uw, 26, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, add.uw, 32, 32 ); + TEST_RR_ZEROSRC12( 37, add.uw, 0 ); + TEST_RR_ZERODEST( 38, add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh1add.S b/isa/rv64uzba/sh1add.S new file mode 100644 index 0000000..1ccaf77 --- /dev/null +++ b/isa/rv64uzba/sh1add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh1add.S +#----------------------------------------------------------------------------- +# +# Test sh1add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh1add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh1add, 0x00000003, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh1add, 0x0000000d, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh1add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh1add, 0xffffffff00000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh1add, 0xfffffffeffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh1add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh1add, 0x00000000fffffffe, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh1add, 0x0000000100007ffd, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh1add, 0xffffffff00007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh1add, 0x00000000ffff7ffe, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh1add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh1add, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh1add, 0xfffffffffffffffd, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh1add, 0x0000000080000001, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 ); + TEST_RR_ZEROSRC12( 37, sh1add, 0 ); + TEST_RR_ZERODEST( 38, sh1add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh1add_uw.S b/isa/rv64uzba/sh1add_uw.S new file mode 100644 index 0000000..78b198d --- /dev/null +++ b/isa/rv64uzba/sh1add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh1add.uw.S +#----------------------------------------------------------------------------- +# +# Test sh1add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh1add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh1add.uw, 0x00000003, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh1add.uw, 0x0000000d, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh1add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh1add.uw, 0x0000000100000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh1add.uw, 0x00000000ffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh1add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh1add.uw, 0x00000000fffffffe, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh1add.uw, 0x0000000100007ffd, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh1add.uw, 0x0000000100007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh1add.uw, 0x00000000ffff7ffe, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh1add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh1add.uw, 0x00000001ffffffff, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh1add.uw, 0x00000001fffffffd, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh1add.uw, 0x0000000080000001, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh1add.uw, 39, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh1add.uw, 41, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add.uw, 41, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add.uw, 41, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add.uw, 41, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add.uw, 41, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh1add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh1add.uw, 64, 32 ); + TEST_RR_ZEROSRC12( 37, sh1add.uw, 0 ); + TEST_RR_ZERODEST( 38, sh1add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh2add.S b/isa/rv64uzba/sh2add.S new file mode 100644 index 0000000..a8756bb --- /dev/null +++ b/isa/rv64uzba/sh2add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh2add.S +#----------------------------------------------------------------------------- +# +# Test sh2add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh2add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh2add, 0x00000005, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh2add, 0x00000013, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh2add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh2add, 0xfffffffe00000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh2add, 0xfffffffdffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh2add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh2add, 0x00000001fffffffc, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh2add, 0x0000000200007ffb, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh2add, 0xfffffffe00007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh2add, 0x00000001ffff7ffc, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh2add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh2add, 0xfffffffffffffffd, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh2add, 0xfffffffffffffffb, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh2add, 0x0000000080000003, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 ); + TEST_RR_ZEROSRC12( 37, sh2add, 0 ); + TEST_RR_ZERODEST( 38, sh2add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh2add_uw.S b/isa/rv64uzba/sh2add_uw.S new file mode 100644 index 0000000..1da3a43 --- /dev/null +++ b/isa/rv64uzba/sh2add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh2add.uw.S +#----------------------------------------------------------------------------- +# +# Test sh2add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh2add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh2add.uw, 0x00000005, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh2add.uw, 0x00000013, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh2add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh2add.uw, 0x0000000200000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh2add.uw, 0x00000001ffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh2add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh2add.uw, 0x00000001fffffffc, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh2add.uw, 0x0000000200007ffb, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh2add.uw, 0x0000000200007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh2add.uw, 0x00000001ffff7ffc, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh2add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh2add.uw, 0x00000003fffffffd, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh2add.uw, 0x00000003fffffffb, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh2add.uw, 0x0000000080000003, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh2add.uw, 65, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh2add.uw, 71, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add.uw, 71, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add.uw, 71, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add.uw, 71, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add.uw, 71, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh2add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh2add.uw, 128, 32 ); + TEST_RR_ZEROSRC12( 37, sh2add.uw, 0 ); + TEST_RR_ZERODEST( 38, sh2add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh3add.S b/isa/rv64uzba/sh3add.S new file mode 100644 index 0000000..086e07a --- /dev/null +++ b/isa/rv64uzba/sh3add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh3add.S +#----------------------------------------------------------------------------- +# +# Test sh3add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh3add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh3add, 0x00000009, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh3add, 0x0000001f, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh3add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh3add, 0xfffffffc00000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh3add, 0xfffffffbffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh3add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh3add, 0x00000003fffffff8, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh3add, 0x0000000400007ff7, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh3add, 0xfffffffc00007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh3add, 0x00000003ffff7ff8, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh3add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh3add, 0xfffffffffffffff9, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh3add, 0xfffffffffffffff7, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh3add, 0x0000000080000007, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 ); + TEST_RR_ZEROSRC12( 37, sh3add, 0 ); + TEST_RR_ZERODEST( 38, sh3add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh3add_uw.S b/isa/rv64uzba/sh3add_uw.S new file mode 100644 index 0000000..f07375f --- /dev/null +++ b/isa/rv64uzba/sh3add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh3add_uw.S +#----------------------------------------------------------------------------- +# +# Test sh3add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh3add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh3add.uw, 0x00000009, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh3add.uw, 0x0000001f, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh3add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh3add.uw, 0x0000000400000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh3add.uw, 0x00000003ffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh3add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh3add.uw, 0x00000003fffffff8, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh3add.uw, 0x0000000400007ff7, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh3add.uw, 0x0000000400007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh3add.uw, 0x00000003ffff7ff8, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh3add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh3add.uw, 0x00000007fffffff9, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh3add.uw, 0x00000007fffffff7, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh3add.uw, 0x0000000080000007, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh3add.uw, 117, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh3add.uw, 131, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add.uw, 131, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add.uw, 131, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add.uw, 131, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add.uw, 131, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh3add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh3add.uw, 256, 32 ); + TEST_RR_ZEROSRC12( 37, sh3add.uw, 0 ); + TEST_RR_ZERODEST( 38, sh3add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/slli_uw.S b/isa/rv64uzba/slli_uw.S new file mode 100644 index 0000000..e60f912 --- /dev/null +++ b/isa/rv64uzba/slli_uw.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slli_uw.S +#----------------------------------------------------------------------------- +# +# Test slli.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slli.uw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, slli.uw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, slli.uw, 0x00000000ffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, slli.uw, 0x00000001fffffffe, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, slli.uw, 0x0000007fffffff80, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, slli.uw, 0x00003fffffffc000, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, slli.uw, 0x7fffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, slli.uw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, slli.uw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, slli.uw, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, slli.uw, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, slli.uw, 0x1090909080000000, 0x0000000021212121, 31 ); + + TEST_IMM_OP( 50, slli.uw, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, slli.uw, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, slli.uw, 0x0909080000000000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slli.uw, 0x00000080, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, slli.uw, 0, 31 ); + TEST_IMM_ZERODEST( 25, slli.uw, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/Makefrag b/isa/rv64uzbb/Makefrag new file mode 100644 index 0000000..2e93897 --- /dev/null +++ b/isa/rv64uzbb/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv64uzbb tests +#----------------------------------------------------------------------- + +rv64uzbb_sc_tests = \ + andn \ + clz clzw \ + cpop cpopw \ + ctz ctzw \ + max maxu \ + min minu \ + orc_b \ + orn \ + rev8 \ + rol rolw \ + ror rorw \ + rori roriw \ + sext_b sext_h \ + xnor \ + zext_h \ + +rv64uzbb_p_tests = $(addprefix rv64uzbb-p-, $(rv64uzbb_sc_tests)) +rv64uzbb_v_tests = $(addprefix rv64uzbb-v-, $(rv64uzbb_sc_tests)) +rv64uzbb_ps_tests = $(addprefix rv64uzbb-ps-, $(rv64uzbb_sc_tests)) + +spike_tests += $(rv64uzbb_p_tests) $(rv64uzbb_v_tests) diff --git a/isa/rv64uzbb/andn.S b/isa/rv64uzbb/andn.S new file mode 100644 index 0000000..be7f032 --- /dev/null +++ b/isa/rv64uzbb/andn.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# andn.S +#----------------------------------------------------------------------------- +# +# Test and instruction. +# This test is forked from and.S +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, andn, 0x00000000000f000f, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, andn, 0x0f000f000f000f00, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, andn, 0x00f000f000f000f0, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, andn, 0x000f000f000f000f, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_EQ_DEST( 8, andn, 0x0000000000000000, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, andn, 0, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, andn, 0x0000000000ff00ff, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, andn, 0 ); + TEST_RR_ZERODEST( 27, andn, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/clz.S b/isa/rv64uzbb/clz.S new file mode 100644 index 0000000..9df6531 --- /dev/null +++ b/isa/rv64uzbb/clz.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clz.S +#----------------------------------------------------------------------------- +# +# Test clz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clz, 64, 0x0000000000000000); + TEST_R_OP( 3, clz, 63, 0x0000000000000001); + TEST_R_OP( 4, clz, 62, 0x0000000000000003); + + TEST_R_OP( 5, clz, 0, 0xffffffffffff8000 ); + TEST_R_OP( 6, clz, 40, 0x0000000000800000 ); + TEST_R_OP( 7, clz, 13, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, clz, 49, 0x0000000000007fff); + TEST_R_OP( 9, clz, 33, 0x000000007fffffff); + TEST_R_OP( 10, clz, 45, 0x000000000007ffff ); + + TEST_R_OP( 11, clz, 0, 0xffffffff80000000); + TEST_R_OP( 12, clz, 8, 0x00ff578f121f5000); + + TEST_R_OP( 13, clz, 0, 0x8000000000000000); + TEST_R_OP( 14, clz, 60, 0x000000000000000e); + TEST_R_OP( 15, clz, 0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clz, 60, 13); + TEST_R_SRC1_EQ_DEST( 17, clz, 60, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clz, 60, 13); + TEST_R_DEST_BYPASS( 29, 1, clz, 59, 19); + TEST_R_DEST_BYPASS( 20, 2, clz, 58, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, clz, 37, 0x00000000070f8000 ); + TEST_R_OP( 22, clz, 36, 0x0000000008008000 ); + TEST_R_OP( 23, clz, 35, 0x0000000018008000 ); + + TEST_R_OP( 24, clz, 30, 0x0000000300007fff); + TEST_R_OP( 25, clz, 29, 0x000000077fffffff); + TEST_R_OP( 26, clz, 28, 0x0000000f0007ffff); + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/clzw.S b/isa/rv64uzbb/clzw.S new file mode 100644 index 0000000..24b659d --- /dev/null +++ b/isa/rv64uzbb/clzw.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clzw.S +#----------------------------------------------------------------------------- +# +# Test clzw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clzw, 32, 0x00000000); + TEST_R_OP( 3, clzw, 31, 0x00000001); + TEST_R_OP( 4, clzw, 30, 0x00000003); + + TEST_R_OP( 5, clzw, 0, 0xffff8000 ); + TEST_R_OP( 6, clzw, 8, 0x00800000 ); + TEST_R_OP( 7, clzw, 0, 0xffff8000 ); + + TEST_R_OP( 8, clzw, 17, 0x00007fff); + TEST_R_OP( 9, clzw, 1, 0x7fffffff); + TEST_R_OP( 10, clzw, 13, 0x0007ffff ); + + TEST_R_OP( 11, clzw, 0, 0x80000000); + TEST_R_OP( 12, clzw, 3, 0x121f5000); + + TEST_R_OP( 13, clzw, 5, 0x04000000); + TEST_R_OP( 14, clzw, 28, 0x0000000e); + TEST_R_OP( 15, clzw, 2, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clzw, 28, 13); + TEST_R_SRC1_EQ_DEST( 17, clzw, 28, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clzw, 28, 13); + TEST_R_DEST_BYPASS( 29, 1, clzw, 27, 19); + TEST_R_DEST_BYPASS( 20, 2, clzw, 26, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + + TEST_R_OP( 21, clzw, 5, 0x070f8000 ); + TEST_R_OP( 22, clzw, 4, 0x08008000 ); + TEST_R_OP( 23, clzw, 3, 0x18008000 ); + + TEST_R_OP( 24, clzw, 17, 0x00007fff); + TEST_R_OP( 25, clzw, 1, 0x7fffffff); + TEST_R_OP( 26, clzw, 13, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/cpop.S b/isa/rv64uzbb/cpop.S new file mode 100644 index 0000000..0083a1a --- /dev/null +++ b/isa/rv64uzbb/cpop.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpop.S +#----------------------------------------------------------------------------- +# +# Test cpop instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpop, 0, 0x0000000000000000); + TEST_R_OP( 3, cpop, 1, 0x0000000000000001); + TEST_R_OP( 4, cpop, 2, 0x0000000000000003); + + TEST_R_OP( 5, cpop, 49, 0xffffffffffff8000 ); + TEST_R_OP( 6, cpop, 1, 0x0000000000800000 ); + TEST_R_OP( 7, cpop, 34, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, cpop, 15, 0x0000000000007fff); + TEST_R_OP( 9, cpop, 31, 0x000000007fffffff); + TEST_R_OP( 10, cpop, 19, 0x000000000007ffff ); + + TEST_R_OP( 11, cpop, 33, 0xffffffff80000000); + TEST_R_OP( 12, cpop, 27, 0x00ff578f121f5000); + + TEST_R_OP( 13, cpop, 1, 0x8000000000000000); + TEST_R_OP( 14, cpop, 3, 0x000000000000000e); + TEST_R_OP( 15, cpop, 11, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpop, 8, 0x00000000007f8000 ); + TEST_R_OP( 22, cpop, 2, 0x0000000000808000 ); + TEST_R_OP( 23, cpop, 3, 0x0000000001808000 ); + + TEST_R_OP( 24, cpop, 17, 0x0000000300007fff); + TEST_R_OP( 25, cpop, 34, 0x000000077fffffff); + TEST_R_OP( 26, cpop, 23, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/cpopw.S b/isa/rv64uzbb/cpopw.S new file mode 100644 index 0000000..7b73882 --- /dev/null +++ b/isa/rv64uzbb/cpopw.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpopw.S +#----------------------------------------------------------------------------- +# +# Test cpopw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpopw, 0, 0x00000000); + TEST_R_OP( 3, cpopw, 1, 0x00000001); + TEST_R_OP( 4, cpopw, 2, 0x00000003); + + TEST_R_OP( 5, cpopw, 17, 0xffff8000 ); + TEST_R_OP( 6, cpopw, 1, 0x00800000 ); + TEST_R_OP( 7, cpopw, 18, 0xffff6000 ); + + TEST_R_OP( 8, cpopw, 15, 0x00007fff); + TEST_R_OP( 9, cpopw, 31, 0x7fffffff); + TEST_R_OP( 10, cpopw, 19, 0x0007ffff ); + + TEST_R_OP( 11, cpopw, 1, 0x80000000); + TEST_R_OP( 12, cpopw, 9, 0x121f5000); + + TEST_R_OP( 13, cpopw, 0, 0x00000000); + TEST_R_OP( 14, cpopw, 3, 0x0000000e); + TEST_R_OP( 15, cpopw, 7, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpopw, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpopw, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpopw, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpopw, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpopw, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpopw, 8, 0x007f8000 ); + TEST_R_OP( 22, cpopw, 2, 0x00808000 ); + TEST_R_OP( 23, cpopw, 3, 0x01808000 ); + + TEST_R_OP( 24, cpopw, 17, 0x30007fff); + TEST_R_OP( 25, cpopw, 30, 0x77ffffff); + TEST_R_OP( 26, cpopw, 19, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/ctz.S b/isa/rv64uzbb/ctz.S new file mode 100644 index 0000000..21b2426 --- /dev/null +++ b/isa/rv64uzbb/ctz.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctz.S +#----------------------------------------------------------------------------- +# +# Test ctz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctz, 64, 0x0000000000000000); + TEST_R_OP( 3, ctz, 0, 0x0000000000000001); + TEST_R_OP( 4, ctz, 0, 0x0000000000000003); + + TEST_R_OP( 5, ctz, 15, 0xffffffffffff8000 ); + TEST_R_OP( 6, ctz, 23, 0x0000000000800000 ); + TEST_R_OP( 7, ctz, 15, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, ctz, 0, 0x0000000000007fff); + TEST_R_OP( 9, ctz, 0, 0x000000007fffffff); + TEST_R_OP( 10, ctz, 0, 0x000000000007ffff ); + + TEST_R_OP( 11, ctz, 31, 0xffffffff80000000); + TEST_R_OP( 12, ctz, 12, 0x00ff578f121f5000); + + TEST_R_OP( 13, ctz, 63, 0x8000000000000000); + TEST_R_OP( 14, ctz, 1, 0x000000000000000e); + TEST_R_OP( 15, ctz, 0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctz, 15, 0x00000000007f8000 ); + TEST_R_OP( 22, ctz, 15, 0x0000000000808000 ); + TEST_R_OP( 23, ctz, 12, 0x0000000001809000 ); + + TEST_R_OP( 24, ctz, 0, 0x0000000300007fff); + TEST_R_OP( 25, ctz, 0, 0x000000077fffffff); + TEST_R_OP( 26, ctz, 0, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/ctzw.S b/isa/rv64uzbb/ctzw.S new file mode 100644 index 0000000..9915bf1 --- /dev/null +++ b/isa/rv64uzbb/ctzw.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctzw.S +#----------------------------------------------------------------------------- +# +# Test ctzw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctzw, 32, 0x00000000); + TEST_R_OP( 3, ctzw, 0, 0x00000001); + TEST_R_OP( 4, ctzw, 0, 0x00000003); + + TEST_R_OP( 5, ctzw, 15, 0xffff8000 ); + TEST_R_OP( 6, ctzw, 23, 0x00800000 ); + TEST_R_OP( 7, ctzw, 15, 0xffff8000 ); + + TEST_R_OP( 8, ctzw, 0, 0x00007fff); + TEST_R_OP( 9, ctzw, 0, 0x7fffffff); + TEST_R_OP( 10, ctzw, 0, 0x0007ffff ); + + TEST_R_OP( 11, ctzw, 31, 0x80000000); + TEST_R_OP( 12, ctzw, 12, 0x121f5000); + + TEST_R_OP( 13, ctzw, 30, 0xc0000000); + TEST_R_OP( 14, ctzw, 1, 0x0000000e); + TEST_R_OP( 15, ctzw, 0, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctzw, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctzw, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctzw, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctzw, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctzw, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctzw, 15, 0x007f8000 ); + TEST_R_OP( 22, ctzw, 15, 0x00808000 ); + TEST_R_OP( 23, ctzw, 12, 0x01809000 ); + + TEST_R_OP( 24, ctzw, 0, 0x00007fff); + TEST_R_OP( 25, ctzw, 0, 0x7fffffff); + TEST_R_OP( 26, ctzw, 0, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/max.S b/isa/rv64uzbb/max.S new file mode 100644 index 0000000..92eb9ad --- /dev/null +++ b/isa/rv64uzbb/max.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# max.S +#----------------------------------------------------------------------------- +# +# Test max instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, max, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, max, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, max, 0x0000000000000007, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, max, 0x0000000000000007, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, max, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, max, 0x0000000000000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, max, 0xffffffffffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, max, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, max, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, max, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, max, 0x0000000000007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, max, 0x000000007fffffff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, max, 0x0000000000000000, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, max, 0x0000000000000001, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, max, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, max, 14, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, max, 13, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, max, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, max, 13, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, max, 14, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, max, 13, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, max, 14, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, max, 13, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, max, 15, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, max, 13, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, max, 16, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, max, 13, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, max, 17, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, max, 13, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, max, 18, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, max, 13, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, max, 19, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, max, 13, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, max, 0, -1 ); + TEST_RR_ZEROSRC2( 36, max, 0, -1 ); + TEST_RR_ZEROSRC12( 37, max, 0 ); + TEST_RR_ZERODEST( 38, max, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/maxu.S b/isa/rv64uzbb/maxu.S new file mode 100644 index 0000000..78c2055 --- /dev/null +++ b/isa/rv64uzbb/maxu.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# maxu.S +#----------------------------------------------------------------------------- +# +# Test maxu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, maxu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, maxu, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, maxu, 0x00000007, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, maxu, 0x00000007, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, maxu, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, maxu, 0x80000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, maxu, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, maxu, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, maxu, 0x7fffffff, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, maxu, 0x7fffffff, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, maxu, 0x80000000, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, maxu, 0xffff8000, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, maxu, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, maxu, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, maxu, 0xffffffff, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, maxu, 14, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, maxu, 13, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, maxu, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, maxu, 13, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, maxu, 14, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, maxu, 13, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, maxu, 14, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, maxu, 13, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, maxu, 15, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, maxu, 13, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, maxu, 16, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, maxu, 13, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, maxu, 17, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, maxu, 13, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, maxu, 18, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, maxu, 13, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, maxu, 19, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, maxu, 13, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, maxu, -1, -1 ); + TEST_RR_ZEROSRC2( 36, maxu, -1, -1 ); + TEST_RR_ZEROSRC12( 37, maxu, 0 ); + TEST_RR_ZERODEST( 38, maxu, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/min.S b/isa/rv64uzbb/min.S new file mode 100644 index 0000000..d2e3e29 --- /dev/null +++ b/isa/rv64uzbb/min.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# min.S +#----------------------------------------------------------------------------- +# +# Test min instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, min, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, min, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, min, 0x0000000000000003, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, min, 0x0000000000000003, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, min, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, min, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, min, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, min, 0x0000000000000000, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, min, 0x0000000000000000, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, min, 0x0000000000007fff, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, min, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, min, 0xffffffffffff8000, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, min, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, min, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, min, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, min, 13, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, min, 11, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, min, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, min, 11, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, min, 13, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, min, 12, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, min, 13, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, min, 11, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, min, 13, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, min, 10, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, min, 13, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, min, 9, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, min, 13, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, min, 8, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, min, 13, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, min, 7, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, min, 13, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, min, 6, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, min, -1, -1 ); + TEST_RR_ZEROSRC2( 36, min, -1, -1 ); + TEST_RR_ZEROSRC12( 37, min, 0 ); + TEST_RR_ZERODEST( 38, min, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/minu.S b/isa/rv64uzbb/minu.S new file mode 100644 index 0000000..f92859a --- /dev/null +++ b/isa/rv64uzbb/minu.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# minu.S +#----------------------------------------------------------------------------- +# +# Test minu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, minu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, minu, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, minu, 0x00000003, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, minu, 0x00000003, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, minu, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, minu, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, minu, 0x80000000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, minu, 0x00000000, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, minu, 0x00000000, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, minu, 0x00007fff, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, minu, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, minu, 0x7fffffff, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, minu, 0x00000000, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, minu, 0x00000001, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, minu, 0xffffffff, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, minu, 13, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, minu, 11, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, minu, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, minu, 11, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, minu, 13, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, minu, 12, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, minu, 13, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, minu, 11, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, minu, 13, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, minu, 10, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, minu, 13, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, minu, 9, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, minu, 13, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, minu, 8, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, minu, 13, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, minu, 7, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, minu, 13, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, minu, 6, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, minu, 0, -1 ); + TEST_RR_ZEROSRC2( 36, minu, 0, -1 ); + TEST_RR_ZEROSRC12( 37, minu, 0 ); + TEST_RR_ZERODEST( 38, minu, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/orc_b.S b/isa/rv64uzbb/orc_b.S new file mode 100644 index 0000000..b236bd3 --- /dev/null +++ b/isa/rv64uzbb/orc_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orc.b.S +#----------------------------------------------------------------------------- +# +# Test orc.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, orc.b, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, orc.b, 0x00000000000000ff, 0x0000000000000001); + TEST_R_OP( 4, orc.b, 0x00000000000000ff, 0x0000000000000003); + + TEST_R_OP( 5, orc.b, 0xffffffffffffff00, 0xffffffffffff8000 ); + TEST_R_OP( 6, orc.b, 0x0000000000ff0000, 0x0000000000800000 ); + TEST_R_OP( 7, orc.b, 0x00ffffffffffff00, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, orc.b, 0x000000000000ffff, 0x0000000000007fff); + TEST_R_OP( 9, orc.b, 0x00000000ffffffff, 0x000000007fffffff); + TEST_R_OP( 10, orc.b, 0x0000000000ffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, orc.b, 0xffffffffff000000, 0xffffffff80000000); + TEST_R_OP( 12, orc.b, 0x00ffffffffffff00, 0x00ff578f121f5000); + + TEST_R_OP( 13, orc.b, 0xff00000000000000, 0x8000000000000000); + TEST_R_OP( 14, orc.b, 0x00000000000000ff, 0x000000000000000e); + TEST_R_OP( 15, orc.b, 0xff0000ffffffffff, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13); + TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13); + TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19); + TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, orc.b, 0x0000000000ffff00, 0x00000000007f8000 ); + TEST_R_OP( 22, orc.b, 0x0000000000ffff00, 0x0000000000808000 ); + TEST_R_OP( 23, orc.b, 0x00000000ffffff00, 0x0000000001808000 ); + + TEST_R_OP( 24, orc.b, 0x000000ff0000ffff, 0x0000000300007fff); + TEST_R_OP( 25, orc.b, 0x000000ffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, orc.b, 0x000000ff00ffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/orn.S b/isa/rv64uzbb/orn.S new file mode 100644 index 0000000..b610007 --- /dev/null +++ b/isa/rv64uzbb/orn.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orn.S +#----------------------------------------------------------------------------- +# +# Test orn instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, orn, 0xffffffffff0fff0f, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, orn, 0x0fff0fff0fff0fff, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, orn, 0xf0fff0fff0fff0ff, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, orn, 0xff0fff0fff0fff0f, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, orn, 0xffffffffffffffff, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, orn, 0x0000000000ff00ff, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, orn, -1, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, orn, -1 ); + TEST_RR_ZERODEST( 27, orn, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rev8.S b/isa/rv64uzbb/rev8.S new file mode 100644 index 0000000..5e65f37 --- /dev/null +++ b/isa/rv64uzbb/rev8.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rev8.S +#----------------------------------------------------------------------------- +# +# Test rev8 instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, rev8, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, rev8, 0x0100000000000000, 0x0000000000000001); + TEST_R_OP( 4, rev8, 0x0300000000000000, 0x0000000000000003); + + TEST_R_OP( 5, rev8, 0x0080ffffffffffff, 0xffffffffffff8000 ); + TEST_R_OP( 6, rev8, 0x0000800000000000, 0x0000000000800000 ); + TEST_R_OP( 7, rev8, 0x0080ffffffff0400, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, rev8, 0xff7f000000000000, 0x0000000000007fff); + TEST_R_OP( 9, rev8, 0xffffff7f00000000, 0x000000007fffffff); + TEST_R_OP( 10, rev8, 0xffff070000000000, 0x000000000007ffff ); + + TEST_R_OP( 11, rev8, 0x00000080ffffffff, 0xffffffff80000000); + TEST_R_OP( 12, rev8, 0x00501f128f57ff00, 0x00ff578f121f5000); + + TEST_R_OP( 13, rev8, 0x0000000000000080, 0x8000000000000000); + TEST_R_OP( 14, rev8, 0x0e00000000000000, 0x000000000000000e); + TEST_R_OP( 15, rev8, 0x41134020030000a0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d00000000000000, 13); + TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b00000000000000, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d00000000000000, 13); + TEST_R_DEST_BYPASS( 29, 1, rev8, 0x1300000000000000, 19); + TEST_R_DEST_BYPASS( 20, 2, rev8, 0x2200000000000000, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, rev8, 0x00807f0000000000, 0x00000000007f8000 ); + TEST_R_OP( 22, rev8, 0x0080800000000000, 0x0000000000808000 ); + TEST_R_OP( 23, rev8, 0x0080800100000000, 0x0000000001808000 ); + + TEST_R_OP( 24, rev8, 0xff7f000003000000, 0x0000000300007fff); + TEST_R_OP( 25, rev8, 0xffffff7f07000000, 0x000000077fffffff); + TEST_R_OP( 26, rev8, 0xffff07000f000000, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rol.S b/isa/rv64uzbb/rol.S new file mode 100644 index 0000000..a69bc05 --- /dev/null +++ b/isa/rv64uzbb/rol.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rol.S +#----------------------------------------------------------------------------- +# +# Test rol instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rol, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rol, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rol, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rol, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rol, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rol, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rol, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rol, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rol, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rol, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rol, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rol, 0x1090909080000000, 0x0000000021212121, 31 ); + + # Verify that rotates only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, rol, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, rol, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, rol, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, rol, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, rol, 0x8000000010909090, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, rol, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, rol, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, rol, 0x0909080000000109, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rol, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rol, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rol, 0 ); + TEST_RR_ZERODEST( 43, rol, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rolw.S b/isa/rv64uzbb/rolw.S new file mode 100644 index 0000000..fdf4674 --- /dev/null +++ b/isa/rv64uzbb/rolw.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rolw.S +#----------------------------------------------------------------------------- +# +# Test rolw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rolw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rolw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rolw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rolw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rolw, 0xffffffff90909090, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rolw, 0x0000000048484848, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rolw, 0xffffffff90909090, 0x0000000021212121, 31 ); + + # Verify that rotates only use bottom five bits + + TEST_RR_OP( 17, rolw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 ); + TEST_RR_OP( 18, rolw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 ); + TEST_RR_OP( 19, rolw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffe7 ); + TEST_RR_OP( 20, rolw, 0x0000000048484848, 0x0000000021212121, 0xffffffffffffffee ); + TEST_RR_OP( 21, rolw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffff ); + + # Verify that rotates ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, rolw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, rolw, 0x0000000023456781, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, rolw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, rolw, 0xffffffff93456789, 0x0000000099345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rolw, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rolw, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rolw, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rolw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rolw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rolw, 0 ); + TEST_RR_ZERODEST( 43, rolw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/ror.S b/isa/rv64uzbb/ror.S new file mode 100644 index 0000000..163333d --- /dev/null +++ b/isa/rv64uzbb/ror.S @@ -0,0 +1,94 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test ror instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, ror, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, ror, 0x8000000000000000, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, ror, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, ror, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, ror, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, ror, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, ror, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, ror, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, ror, 0x8000000010909090, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, ror, 0x4200000000424242, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, ror, 0x8484000000008484, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, ror, 0x4242424200000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, ror, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, ror, 0x8000000010909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, ror, 0x4200000000424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, ror, 0x8484000000008484, 0x0000000021212121, 0xffffffffffffffce ); + + TEST_RR_OP( 21, ror, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, ror, 0x0000000000000002, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, ror, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, ror, 0x0004242424200000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, ror, 0x0200000000000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, ror, 0x0004000000000000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, ror, 0x6000000000000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, ror, 0, 15 ); + TEST_RR_ZEROSRC2( 41, ror, 32, 32 ); + TEST_RR_ZEROSRC12( 42, ror, 0 ); + TEST_RR_ZERODEST( 43, ror, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rori.S b/isa/rv64uzbb/rori.S new file mode 100644 index 0000000..153f8e6 --- /dev/null +++ b/isa/rv64uzbb/rori.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, rori, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, rori, 0x8000000000000000, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, rori, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, rori, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, rori, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, rori, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, rori, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, rori, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, rori, 0x8000000010909090, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, rori, 0x4200000000424242, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, rori, 0x8484000000008484, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, rori, 0x4242424200000000, 0x0000000021212121, 31 ); + + TEST_IMM_OP( 17, rori, 0x0000000000000002, 0x0000000000000001, 63 ); + TEST_IMM_OP( 18, rori, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 19, rori, 0x0004242424200000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x0200000000000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, rori, 0, 31 ); + TEST_IMM_ZERODEST( 28, rori, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/roriw.S b/isa/rv64uzbb/roriw.S new file mode 100644 index 0000000..44f3819 --- /dev/null +++ b/isa/rv64uzbb/roriw.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, roriw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, roriw, 0xffffffff80000000, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, roriw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, roriw, 0xffffffff90909090, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, roriw, 0x0000000042424242, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, roriw, 0xffffffff84848484, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, roriw, 0x0000000042424242, 0x0000000021212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, roriw, 0x0000000002000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, roriw, 0, 31 ); + TEST_IMM_ZERODEST( 28, roriw, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rorw.S b/isa/rv64uzbb/rorw.S new file mode 100644 index 0000000..de11c3c --- /dev/null +++ b/isa/rv64uzbb/rorw.S @@ -0,0 +1,91 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rorw.S +#----------------------------------------------------------------------------- +# +# Test rorw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rorw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rorw, 0xffffffff80000000, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rorw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rorw, 0xffffffff90909090, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rorw, 0x0000000042424242, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rorw, 0xffffffff84848484, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rorw, 0x0000000042424242, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, rorw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, rorw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, rorw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, rorw, 0xffffffff84848484, 0x0000000021212121, 0xffffffffffffffce ); + + TEST_RR_OP( 21, rorw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rorw, 0x0000000002000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rorw, 0x0000000000040000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rorw, 0x0000000060000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rorw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rorw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rorw, 0 ); + TEST_RR_ZERODEST( 43, rorw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/sext_b.S b/isa/rv64uzbb/sext_b.S new file mode 100644 index 0000000..8acf86a --- /dev/null +++ b/isa/rv64uzbb/sext_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_b.S +#----------------------------------------------------------------------------- +# +# Test sext.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, sext.b, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, sext.b, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, sext.b, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, sext.b, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_R_OP( 6, sext.b, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, sext.b, 0x0000000000000000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, sext.b, 0xffffffffffffffff, 0x0000000000007fff); + TEST_R_OP( 9, sext.b, 0xffffffffffffffff, 0x000000007fffffff); + TEST_R_OP( 10, sext.b, 0xffffffffffffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, sext.b, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, sext.b, 0x0000000000000000, 0x00ff578f121f5000); + + TEST_R_OP( 13, sext.b, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, sext.b, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, sext.b, 0x0000000000000041, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, sext.b, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, sext.b, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, sext.b, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, sext.b, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, sext.b, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, sext.b, 0x0000000000000000, 0x00000000007f8000 ); + TEST_R_OP( 22, sext.b, 0x0000000000000000, 0x0000000000808000 ); + TEST_R_OP( 23, sext.b, 0x0000000000000000, 0x0000000001808000 ); + + TEST_R_OP( 24, sext.b, 0xffffffffffffffff, 0x0000000300007fff); + TEST_R_OP( 25, sext.b, 0xffffffffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, sext.b, 0xffffffffffffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/sext_h.S b/isa/rv64uzbb/sext_h.S new file mode 100644 index 0000000..59cf386 --- /dev/null +++ b/isa/rv64uzbb/sext_h.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_h.S +#----------------------------------------------------------------------------- +# +# Test sext.h instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, sext.h, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, sext.h, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, sext.h, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, sext.h, 0xffffffffffff8000, 0xffffffffffff8000 ); + TEST_R_OP( 6, sext.h, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, sext.h, 0xffffffffffff8000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, sext.h, 0x0000000000007fff, 0x0000000000007fff); + TEST_R_OP( 9, sext.h, 0xffffffffffffffff, 0x000000007fffffff); + TEST_R_OP( 10, sext.h, 0xffffffffffffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, sext.h, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, sext.h, 0x0000000000005000, 0x00ff578f121f5000); + + TEST_R_OP( 13, sext.h, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, sext.h, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, sext.h, 0x0000000000001341, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, sext.h, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, sext.h, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, sext.h, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, sext.h, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, sext.h, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, sext.h, 0xffffffffffff8000, 0x00000000007f8000 ); + TEST_R_OP( 22, sext.h, 0xffffffffffff8000, 0x0000000000808000 ); + TEST_R_OP( 23, sext.h, 0xffffffffffff8000, 0x0000000001808000 ); + + TEST_R_OP( 24, sext.h, 0x0000000000007fff, 0x0000000300007fff); + TEST_R_OP( 25, sext.h, 0xffffffffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, sext.h, 0xffffffffffffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/xnor.S b/isa/rv64uzbb/xnor.S new file mode 100644 index 0000000..5a74f86 --- /dev/null +++ b/isa/rv64uzbb/xnor.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# xnor.S +#----------------------------------------------------------------------------- +# +# Test xnor instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, xnor, 0xffffffffff00ff00, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, xnor, 0x00ff00ff00ff00ff, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, xnor, 0xf00ff00ff00ff00f, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, xnor, 0xff00ff00ff00ff00, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, xnor, 0xffffffffffffffff, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, xnor, 0x0000000000ff00ff, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, xnor, 0xffffffffff00ff00, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, xnor, -1 ); + TEST_RR_ZERODEST( 27, xnor, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/zext_h.S b/isa/rv64uzbb/zext_h.S new file mode 100644 index 0000000..baa0b7a --- /dev/null +++ b/isa/rv64uzbb/zext_h.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_h.S +#----------------------------------------------------------------------------- +# +# Test zext.h instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, zext.h, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, zext.h, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, zext.h, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, zext.h, 0x0000000000008000, 0xffffffffffff8000 ); + TEST_R_OP( 6, zext.h, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, zext.h, 0x0000000000008000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, zext.h, 0x0000000000007fff, 0x0000000000007fff); + TEST_R_OP( 9, zext.h, 0x000000000000ffff, 0x000000007fffffff); + TEST_R_OP( 10, zext.h, 0x000000000000ffff, 0x000000000007ffff ); + + TEST_R_OP( 11, zext.h, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, zext.h, 0x0000000000005000, 0x00ff578f121f5000); + + TEST_R_OP( 13, zext.h, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, zext.h, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, zext.h, 0x0000000000001341, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, zext.h, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, zext.h, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, zext.h, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, zext.h, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, zext.h, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, zext.h, 0x0000000000008000, 0x00000000007f8000 ); + TEST_R_OP( 22, zext.h, 0x0000000000008000, 0x0000000000808000 ); + TEST_R_OP( 23, zext.h, 0x0000000000008000, 0x0000000001808000 ); + + TEST_R_OP( 24, zext.h, 0x0000000000007fff, 0x0000000300007fff); + TEST_R_OP( 25, zext.h, 0x000000000000ffff, 0x000000077fffffff); + TEST_R_OP( 26, zext.h, 0x000000000000ffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbc/Makefrag b/isa/rv64uzbc/Makefrag new file mode 100644 index 0000000..01ce4e2 --- /dev/null +++ b/isa/rv64uzbc/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv64uzbc tests +#----------------------------------------------------------------------- + +rv64uzbc_sc_tests = \ + clmul \ + clmulh \ + clmulr \ + +rv64uzbc_p_tests = $(addprefix rv64uzbc-p-, $(rv64uzbc_sc_tests)) +rv64uzbc_v_tests = $(addprefix rv64uzbc-v-, $(rv64uzbc_sc_tests)) +rv64uzbc_ps_tests = $(addprefix rv64uzbc-ps-, $(rv64uzbc_sc_tests)) + +spike_tests += $(rv64uzbc_p_tests) $(rv64uzbc_v_tests) diff --git a/isa/rv64uzbc/clmul.S b/isa/rv64uzbc/clmul.S new file mode 100644 index 0000000..c147791 --- /dev/null +++ b/isa/rv64uzbc/clmul.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmul.S +#----------------------------------------------------------------------------- +# +# Test clmul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmul, 0x0000000000005a00, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, clmul, 0x0000000000005b40, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, clmul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmul, 0x00000009, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, clmul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, clmul, 0x5555400000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, clmul, 0xfffffffffffc324f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, clmul, 0xfffffffffffc324f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmul, 0x51, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmul, 0x62, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmul, 0 ); + TEST_RR_ZERODEST( 29, clmul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbc/clmulh.S b/isa/rv64uzbc/clmulh.S new file mode 100644 index 0000000..c5eaf65 --- /dev/null +++ b/isa/rv64uzbc/clmulh.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulh.S +#----------------------------------------------------------------------------- +# +# Test clmulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulh, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, clmulh, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, clmulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, clmulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulh, 0x555555557fffd555, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, clmulh, 0x00000000000133cd, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, clmulh, 0x00000000000133cd, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulh, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulh, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulh, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulh, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulh, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulh, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulh, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulh, 0 ); + TEST_RR_ZERODEST( 29, clmulh, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbc/clmulr.S b/isa/rv64uzbc/clmulr.S new file mode 100644 index 0000000..d2f86df --- /dev/null +++ b/isa/rv64uzbc/clmulr.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulr.S +#----------------------------------------------------------------------------- +# +# Test clmulr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulr, 0x0000000000002400, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, clmulr, 0x0000000000002480, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, clmulr, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulr, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulr, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulr, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, clmulr, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulr, 0xaaaaaaaaffffaaaa, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, clmulr, 0x000000000002679b, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, clmulr, 0x000000000002679b, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulr, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulr, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulr, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulr, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulr, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulr, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulr, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulr, 0 ); + TEST_RR_ZERODEST( 29, clmulr, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/Makefrag b/isa/rv64uzbs/Makefrag new file mode 100644 index 0000000..3264b4d --- /dev/null +++ b/isa/rv64uzbs/Makefrag @@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv64uzbs tests +#----------------------------------------------------------------------- + +rv64uzbs_sc_tests = \ + bclr bclri \ + bext bexti \ + binv binvi \ + bset bseti \ + +rv64uzbs_p_tests = $(addprefix rv64uzbs-p-, $(rv64uzbs_sc_tests)) +rv64uzbs_v_tests = $(addprefix rv64uzbs-v-, $(rv64uzbs_sc_tests)) +rv64uzbs_ps_tests = $(addprefix rv64uzbs-ps-, $(rv64uzbs_sc_tests)) + +spike_tests += $(rv64uzbs_p_tests) $(rv64uzbs_v_tests) diff --git a/isa/rv64uzbs/bclr.S b/isa/rv64uzbs/bclr.S new file mode 100644 index 0000000..75d48de --- /dev/null +++ b/isa/rv64uzbs/bclr.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bclr.S +#----------------------------------------------------------------------------- +# +# Test bclr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bclr, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, bclr, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, bclr, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, bclr, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, bclr, 0xfffffffff7ffffff, 0xffffffffffffffff, 27 ); + + TEST_RR_OP( 12, bclr, 0x21212120, 0x21212121, 0 ); + TEST_RR_OP( 13, bclr, 0x21212121, 0x21212121, 1 ); + TEST_RR_OP( 14, bclr, 0x21212121, 0x21212121, 7 ); + TEST_RR_OP( 15, bclr, 0x21210121, 0x21212121, 13 ); + TEST_RR_OP( 16, bclr, 0x04848484, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bclr, 0x21212120, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bclr, 0x21212121, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bclr, 0x21212121, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bclr, 0x84848484, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bclr, 0x4484848421212121, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bclr, 0x0000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bclr, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bclr, 0xfffff7ff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bclr, 0x00000001, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bclr, 0x00001551, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bclr, 3, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bclr, 0xff00fe00, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bclr, 0, 15 ); + TEST_RR_ZEROSRC2( 41, bclr, 32, 32 ); + TEST_RR_ZEROSRC12( 42, bclr, 0 ); + TEST_RR_ZERODEST( 43, bclr, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bclri.S b/isa/rv64uzbs/bclri.S new file mode 100644 index 0000000..3d4fdf9 --- /dev/null +++ b/isa/rv64uzbs/bclri.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bclri.S +#----------------------------------------------------------------------------- +# +# Test bclri instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bclri, 0xff00ff00, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bclri, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bclri, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, bclri, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, bclri, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, bclri, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, bclri, 0xfffffffff7ffffff, 0xffffffffffffffff, 27 ); + + TEST_IMM_OP( 12, bclri, 0x21212120, 0x21212121, 0 ); + TEST_IMM_OP( 13, bclri, 0x21212121, 0x21212121, 1 ); + TEST_IMM_OP( 14, bclri, 0x21212121, 0x21212121, 7 ); + TEST_IMM_OP( 15, bclri, 0x21210121, 0x21212121, 13 ); + TEST_IMM_OP( 16, bclri, 0x04848484, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bclri, 0x0000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bclri, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bclri, 0xfffff7ff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bclri, 0x00000001, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_DEST_BYPASS( 19, 1, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bclri, 0, 31 ); + TEST_IMM_ZERODEST( 25, bclri, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bext.S b/isa/rv64uzbs/bext.S new file mode 100644 index 0000000..0440741 --- /dev/null +++ b/isa/rv64uzbs/bext.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bext.S +#----------------------------------------------------------------------------- +# +# Test bext instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bext, 0, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bext, 1, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bext, 1, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bext, 1, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, bext, 1, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, bext, 1, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, bext, 1, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, bext, 1, 0xffffffffffffffff, 27 ); + + TEST_RR_OP( 12, bext, 1, 0x21212121, 0 ); + TEST_RR_OP( 13, bext, 0, 0x21212121, 1 ); + TEST_RR_OP( 14, bext, 0, 0x21212121, 7 ); + TEST_RR_OP( 15, bext, 1, 0x21212121, 13 ); + TEST_RR_OP( 16, bext, 1, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bext, 1, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bext, 0, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bext, 0, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bext, 0, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bext, 1, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bext, 0, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bext, 1, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bext, 1, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bext, 0, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bext, 1, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bext, 0, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bext, 1, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bext, 1, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bext, 1, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bext, 1, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bext, 0, 15 ); + TEST_RR_ZEROSRC2( 41, bext, 0, 32 ); + TEST_RR_ZEROSRC12( 42, bext, 0 ); + TEST_RR_ZERODEST( 43, bext, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bexti.S b/isa/rv64uzbs/bexti.S new file mode 100644 index 0000000..19c9ed5 --- /dev/null +++ b/isa/rv64uzbs/bexti.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bexti.S +#----------------------------------------------------------------------------- +# +# Test bexti instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bexti, 0, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bexti, 1, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bexti, 1, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, bexti, 1, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, bexti, 1, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, bexti, 1, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, bexti, 1, 0xffffffffffffffff, 27 ); + + TEST_IMM_OP( 12, bexti, 1, 0x21212121, 0 ); + TEST_IMM_OP( 13, bexti, 0, 0x21212121, 1 ); + TEST_IMM_OP( 14, bexti, 0, 0x21212121, 7 ); + TEST_IMM_OP( 15, bexti, 1, 0x21212121, 13 ); + TEST_IMM_OP( 16, bexti, 1, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bexti, 0, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bexti, 1, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bexti, 1, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bexti, 0, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_DEST_BYPASS( 19, 1, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bexti, 0, 31 ); + TEST_IMM_ZERODEST( 25, bexti, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/binv.S b/isa/rv64uzbs/binv.S new file mode 100644 index 0000000..853b398 --- /dev/null +++ b/isa/rv64uzbs/binv.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# binv.S +#----------------------------------------------------------------------------- +# +# Test binv instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, binv, 0x0000000000000000, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, binv, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, binv, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, binv, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, binv, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, binv, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, binv, 0xffffffff7fffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, binv, 0x0000000021212120, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, binv, 0x0000000021212123, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, binv, 0x00000000212121a1, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, binv, 0x0000000021216121, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, binv, 0x00000000a1212121, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, binv, 0x0000000021212120, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, binv, 0x0000000021212123, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, binv, 0x00000000212121a1, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, binv, 0x0000000021216121, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, binv, 0x8000000021212121, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, binv, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, binv, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, binv, 0x0000080021212121, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, binv, 0x00000081, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, binv, 0x00004001, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, binv, 11, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, binv, 0x00008000, 15 ); + TEST_RR_ZEROSRC2( 41, binv, 33, 32 ); + TEST_RR_ZEROSRC12( 42, binv, 1 ); + TEST_RR_ZERODEST( 43, binv, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/binvi.S b/isa/rv64uzbs/binvi.S new file mode 100644 index 0000000..07af1f4 --- /dev/null +++ b/isa/rv64uzbs/binvi.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# binvi.S +#----------------------------------------------------------------------------- +# +# Test binvi instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, binvi, 0x0000000000000000, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, binvi, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, binvi, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, binvi, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, binvi, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, binvi, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, binvi, 0xffffffff7fffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, binvi, 0x0000000021212120, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, binvi, 0x0000000021212123, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, binvi, 0x00000000212121a1, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, binvi, 0x0000000021216121, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, binvi, 0x00000000a1212121, 0x0000000021212121, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, binvi, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, binvi, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, binvi, 0x0000080021212121, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, binvi, 0x00000081, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + + TEST_IMM_ZEROSRC1( 24, binvi, 0x00008000, 15 ); + TEST_IMM_ZERODEST( 25, binvi, 1024, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bset.S b/isa/rv64uzbs/bset.S new file mode 100644 index 0000000..ee80b60 --- /dev/null +++ b/isa/rv64uzbs/bset.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bset.S +#----------------------------------------------------------------------------- +# +# Test bset instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bset, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 8, bset, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_RR_OP( 9, bset, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_OP( 10, bset, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_OP( 11, bset, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_OP( 12, bset, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, bset, 0x21212123, 0x21212121, 1 ); + TEST_RR_OP( 14, bset, 0x212121a1, 0x21212121, 7 ); + TEST_RR_OP( 15, bset, 0x21212121, 0x21212121, 13 ); + TEST_RR_OP( 16, bset, 0x84848484, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bset, 0x21212121, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bset, 0x21212123, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bset, 0x212121a1, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bset, 0x8484c484, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bset, 0xc484848421212121, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bset, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bset, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bset, 0xffffffff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bset, 0x00000081, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bset, 0x00005551, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bset, 11, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bset, 0x00008000, 15 ); + TEST_RR_ZEROSRC2( 41, bset, 33, 32 ); + TEST_RR_ZEROSRC12( 42, bset, 1 ); + TEST_RR_ZERODEST( 43, bset, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bseti.S b/isa/rv64uzbs/bseti.S new file mode 100644 index 0000000..35a5501 --- /dev/null +++ b/isa/rv64uzbs/bseti.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bset.S +#----------------------------------------------------------------------------- +# +# Test bset instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bset, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 8, bset, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_IMM_OP( 9, bset, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_OP( 10, bset, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_OP( 11, bset, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 12, bset, 0x21212121, 0x21212121, 0 ); + TEST_IMM_OP( 13, bset, 0x21212123, 0x21212121, 1 ); + TEST_IMM_OP( 14, bset, 0x212121a1, 0x21212121, 7 ); + TEST_IMM_OP( 15, bset, 0x21212121, 0x21212121, 13 ); + TEST_IMM_OP( 16, bset, 0x84848484, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bset, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bset, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bset, 0xffffffff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bset, 0x00000081, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_IMM_DEST_BYPASS( 19, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_IMM_DEST_BYPASS( 20, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bset, 0x00008000, 15 ); + TEST_IMM_ZERODEST( 25, bset, 1024, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |