Merge rv32ua tests into rv64ua

9 files changed, 23 insertions, 365 deletions

diff --git a/isa/rv32ua/amoadd_w.S b/isa/rv32ua/amoadd_w.S
index 975ae1d..df4560d 100644
--- a/isa/rv32ua/amoadd_w.S
+++ b/isa/rv32ua/amoadd_w.S
@@ -1,65 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# amoadd_w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoadd.w instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  TEST_CASE(2, a4, 0x80000000, \
-    li a0, 0x80000000; \
-    li a1, 0xfffff800; \
-    la a3, amo_operand; \
-    sw a0, 0(a3); \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    amoadd.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
-
-  # try again after a cache miss
-  TEST_CASE(4, a4, 0x7ffff800, \
-    li  a1, 0x80000000; \
-    li  a4, 16384; \
-    add a5, a3, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    amoadd.w a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(5, a5, 0xfffff800, lw a5, 0(a3))
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-    .bss
-    .align 3
-amo_operand:
-    .dword 0
-    .skip 65536
+#include "../rv64ua/amoadd_w.S"
diff --git a/isa/rv32ua/amoand_w.S b/isa/rv32ua/amoand_w.S
index 7c989c2..b824483 100644
--- a/isa/rv32ua/amoand_w.S
+++ b/isa/rv32ua/amoand_w.S
@@ -1,65 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# amoand.w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoand.w instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  TEST_CASE(2, a4, 0x80000000, \
-    li a0, 0x80000000; \
-    li a1, 0xfffff800; \
-    la a3, amo_operand; \
-    sw a0, 0(a3); \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    amoand.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
-  # try again after a cache miss
-  TEST_CASE(4, a4, 0x80000000, \
-    li  a1, 0x80000000; \
-    li  a4, 16384; \
-    add a5, a3, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    amoand.w a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3))
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-  .bss
-  .align 3
-amo_operand:
-  .dword 0
-  .skip 65536
+#include "../rv64ua/amoand_w.S"
diff --git a/isa/rv32ua/amomax_w.S b/isa/rv32ua/amomax_w.S
index 698cf26..899d7d6 100644
--- a/isa/rv32ua/amomax_w.S
+++ b/isa/rv32ua/amomax_w.S
@@ -1,49 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# amomax_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomax.w instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  TEST_CASE(2, a4, 0x80000000, \
-    li a0, 0x80000000; \
-    li a1, 0xfffff800; \
-    la a3, amo_operand; \
-    sw a0, 0(a3); \
-    amomax.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
-
-  TEST_CASE(4, a4, 0, \
-    li a1, 1; \
-    sw x0, 0(a3); \
-    amomax.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(5, a5, 1, lw a5, 0(a3))
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-  .bss
-  .align 3
-amo_operand:
-  .dword 0
-  .skip 65536
+#include "../rv64ua/amomax_w.S"
diff --git a/isa/rv32ua/amomaxu_w.S b/isa/rv32ua/amomaxu_w.S
index 27c4ddf..662f023 100644
--- a/isa/rv32ua/amomaxu_w.S
+++ b/isa/rv32ua/amomaxu_w.S
@@ -1,49 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# amomaxu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomaxu.w instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  TEST_CASE(2, a4, 0x80000000, \
-    li a0, 0x80000000; \
-    li a1, 0xfffff800; \
-    la a3, amo_operand; \
-    sw a0, 0(a3); \
-    amomaxu.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
-
-  TEST_CASE(4, a4, 0, \
-    li a1, 0xffffffff; \
-    sw x0, 0(a3); \
-    amomaxu.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-  .bss
-  .align 3
-amo_operand:
-  .dword 0
-  .skip 65536
+#include "../rv64ua/amomaxu_w.S"
diff --git a/isa/rv32ua/amomin_w.S b/isa/rv32ua/amomin_w.S
index a6a0947..cbd88e6 100644
--- a/isa/rv32ua/amomin_w.S
+++ b/isa/rv32ua/amomin_w.S
@@ -1,49 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# amomin_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomin.w instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  TEST_CASE(2, a4, 0x80000000, \
-    li a0, 0x80000000; \
-    li a1, 0xfffff800; \
-    la a3, amo_operand; \
-    sw a0, 0(a3); \
-    amomin.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
-  TEST_CASE(4, a4, 0, \
-    li a1, 0xffffffff; \
-    sw x0, 0(a3); \
-    amomin.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-  .bss
-  .align 3
-amo_operand:
-  .dword 0
-  .skip 65536
+#include "../rv64ua/amomin_w.S"
diff --git a/isa/rv32ua/amominu_w.S b/isa/rv32ua/amominu_w.S
index ce06e1c..acb0d79 100644
--- a/isa/rv32ua/amominu_w.S
+++ b/isa/rv32ua/amominu_w.S
@@ -1,49 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# amominu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amominu.w instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  TEST_CASE(2, a4, 0x80000000, \
-    li a0, 0x80000000; \
-    li a1, 0xfffff800; \
-    la a3, amo_operand; \
-    sw a0, 0(a3); \
-    amominu.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
-  TEST_CASE(4, a4, 0, \
-    li a1, 0xffffffff; \
-    sw x0, 0(a3); \
-    amominu.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(5, a5, 0, lw a5, 0(a3))
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-  .bss
-  .align 3
-amo_operand:
-  .dword 0
-  .skip 65536
+#include "../rv64ua/amominu_w.S"
diff --git a/isa/rv32ua/amoor_w.S b/isa/rv32ua/amoor_w.S
index 0988c66..0a2a57d 100644
--- a/isa/rv32ua/amoor_w.S
+++ b/isa/rv32ua/amoor_w.S
@@ -1,65 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# amoor.w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoor.w instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  TEST_CASE(2, a4, 0x80000000, \
-    li a0, 0x80000000; \
-    li a1, 0xfffff800; \
-    la a3, amo_operand; \
-    sw a0, 0(a3); \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    amoor.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
-
-  # try again after a cache miss
-  TEST_CASE(4, a4, 0xfffff800, \
-    li  a1, 1; \
-    li  a4, 16384; \
-    add a5, a3, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    amoor.w a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(5, a5, 0xfffff801, lw a5, 0(a3))
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-  .bss
-  .align 3
-amo_operand:
-  .dword 0
-  .skip 65536
+#include "../rv64ua/amoor_w.S"
diff --git a/isa/rv64ua/amoand_w.S b/isa/rv64ua/amoand_w.S
index a843888..d8f888a 100644
--- a/isa/rv64ua/amoand_w.S
+++ b/isa/rv64ua/amoand_w.S
@@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN
     li a0, 0xffffffff80000000; \
     li a1, 0xfffffffffffff800; \
     la a3, amo_operand; \
-    sd a0, 0(a3); \
+    sw a0, 0(a3); \
     nop; nop; nop; nop; \
     nop; nop; nop; nop; \
     nop; nop; nop; nop; \
diff --git a/isa/rv64ua/amoor_w.S b/isa/rv64ua/amoor_w.S
index 47978ba..c0a1c69 100644
--- a/isa/rv64ua/amoor_w.S
+++ b/isa/rv64ua/amoor_w.S
@@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN
     li a0, 0xffffffff80000000; \
     li a1, 0xfffffffffffff800; \
     la a3, amo_operand; \
-    sd a0, 0(a3); \
+    sw a0, 0(a3); \
     nop; nop; nop; nop; \
     nop; nop; nop; nop; \
     nop; nop; nop; nop; \