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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-21 16:47:04 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-21 16:47:04 -0700 |
| commit | d2bd84a096a97ff4b8f41035c984991d0df922c1 (patch) | |
| tree | 01a3f8756341a0ff1b376dd8bd0ed0b30c1a3fb6 /isa | |
| parent | 96ef658f1fce0f1b4cce468ad7fa3ff453b9ebac (diff) | |
| download | riscv-tests-d2bd84a096a97ff4b8f41035c984991d0df922c1.zip riscv-tests-d2bd84a096a97ff4b8f41035c984991d0df922c1.tar.gz riscv-tests-d2bd84a096a97ff4b8f41035c984991d0df922c1.tar.bz2 | |
Allow supervisor access to user pages in dirty-bit test
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64si/dirty.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S index e3a7987..06c9780 100644 --- a/isa/rv64si/dirty.S +++ b/isa/rv64si/dirty.S @@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN or a2, a2, a0 csrw sptbr, a1 sfence.vma - li a1, (MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM csrs mstatus, a1 la a1, 1f - DRAM_BASE csrw mepc, a1 |