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| author | Howard Mao <zhehao.mao@gmail.com> | 2016-07-22 14:20:28 -0700 |
|---|---|---|
| committer | Howard Mao <zhehao.mao@gmail.com> | 2016-07-22 14:20:35 -0700 |
| commit | 8ad0c87b54dc1b52548c62834d2597b573e60848 (patch) | |
| tree | a1b55ee3a66b134b2cba3d196e6e4cbee0ccbe4b /isa | |
| parent | 702d796abdf0e91fa942a46474af9e1ebb1ff343 (diff) | |
| download | riscv-tests-8ad0c87b54dc1b52548c62834d2597b573e60848.zip riscv-tests-8ad0c87b54dc1b52548c62834d2597b573e60848.tar.gz riscv-tests-8ad0c87b54dc1b52548c62834d2597b573e60848.tar.bz2 | |
skip user-mode trap tests in rv32mi/rv64mi-p-csr if no user mode
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64si/csr.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index 3858daa..68f6fb1 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -34,6 +34,14 @@ RVTEST_CODE_BEGIN TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0); TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch); +#ifdef __MACHINE_MODE + # Figure out if 'U' is set in misa + csrr a0, misa # a0 = csr(misa) + srli a0, a0, 20 # a0 = a0 >> 20 + andi a0, a0, 1 # a0 = a0 & 1 + beqz a0, finish # if no user mode, skip the rest of these checks +#endif + # Make sure writing the cycle counter causes an exception. # Don't run in supervisor, as we don't delegate illegal instruction traps. #ifdef __MACHINE_MODE @@ -56,6 +64,7 @@ RVTEST_CODE_BEGIN TEST_CASE(11, x0, 0, nop) #endif +finish: RVTEST_PASS # We should only fall through to this if scall failed. |