correctly set SR_EA bit for all vector physical tests

60 files changed, 61 insertions, 59 deletions

diff --git a/isa/macros/vector/test_macros.h b/isa/macros/vector/test_macros.h
index 6cfda12..59e9e77 100644
--- a/isa/macros/vector/test_macros.h
+++ b/isa/macros/vector/test_macros.h
@@ -1,6 +1,8 @@
 #ifndef __TEST_MACROS_VECTOR_H
 #define __TEST_MACROS_VECTOR_H
 
+#undef EXTRA_INIT
+#define EXTRA_INIT RVTEST_VEC_ENABLE
 
 #-----------------------------------------------------------------------
 # Helper macros
diff --git a/isa/rv64uv/amoadd_d.S b/isa/rv64uv/amoadd_d.S
index ce3c6a6..68b0ba1 100644
--- a/isa/rv64uv/amoadd_d.S
+++ b/isa/rv64uv/amoadd_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amoadd_w.S b/isa/rv64uv/amoadd_w.S
index 2bf010f..ba798ef 100644
--- a/isa/rv64uv/amoadd_w.S
+++ b/isa/rv64uv/amoadd_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amoand_d.S b/isa/rv64uv/amoand_d.S
index 2652fbe..b2dc699 100644
--- a/isa/rv64uv/amoand_d.S
+++ b/isa/rv64uv/amoand_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amoand_w.S b/isa/rv64uv/amoand_w.S
index 93f660f..726033d 100644
--- a/isa/rv64uv/amoand_w.S
+++ b/isa/rv64uv/amoand_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amomax_d.S b/isa/rv64uv/amomax_d.S
index 97a5cf4..aafdf75 100644
--- a/isa/rv64uv/amomax_d.S
+++ b/isa/rv64uv/amomax_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amomax_w.S b/isa/rv64uv/amomax_w.S
index f89bed6..0308991 100644
--- a/isa/rv64uv/amomax_w.S
+++ b/isa/rv64uv/amomax_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amomaxu_d.S b/isa/rv64uv/amomaxu_d.S
index 679c04d..95d8fce 100644
--- a/isa/rv64uv/amomaxu_d.S
+++ b/isa/rv64uv/amomaxu_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amomaxu_w.S b/isa/rv64uv/amomaxu_w.S
index 342d931..feac563 100644
--- a/isa/rv64uv/amomaxu_w.S
+++ b/isa/rv64uv/amomaxu_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amomin_d.S b/isa/rv64uv/amomin_d.S
index c8dd43e..6fd9d27 100644
--- a/isa/rv64uv/amomin_d.S
+++ b/isa/rv64uv/amomin_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amomin_w.S b/isa/rv64uv/amomin_w.S
index 0633ba7..44260f2 100644
--- a/isa/rv64uv/amomin_w.S
+++ b/isa/rv64uv/amomin_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amominu_d.S b/isa/rv64uv/amominu_d.S
index 13fa5f2..3f5f7ab 100644
--- a/isa/rv64uv/amominu_d.S
+++ b/isa/rv64uv/amominu_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amominu_w.S b/isa/rv64uv/amominu_w.S
index 329b354..56f3a7d 100644
--- a/isa/rv64uv/amominu_w.S
+++ b/isa/rv64uv/amominu_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amoor_d.S b/isa/rv64uv/amoor_d.S
index 800550d..76d553c 100644
--- a/isa/rv64uv/amoor_d.S
+++ b/isa/rv64uv/amoor_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amoor_w.S b/isa/rv64uv/amoor_w.S
index 7fa683a..9d0bd2f 100644
--- a/isa/rv64uv/amoor_w.S
+++ b/isa/rv64uv/amoor_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amoswap_d.S b/isa/rv64uv/amoswap_d.S
index 6a33b1f..df98556 100644
--- a/isa/rv64uv/amoswap_d.S
+++ b/isa/rv64uv/amoswap_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/amoswap_w.S b/isa/rv64uv/amoswap_w.S
index 3ba51cb..c068569 100644
--- a/isa/rv64uv/amoswap_w.S
+++ b/isa/rv64uv/amoswap_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/beq.S b/isa/rv64uv/beq.S
index aa6f2ff..c2f7a56 100644
--- a/isa/rv64uv/beq.S
+++ b/isa/rv64uv/beq.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------
diff --git a/isa/rv64uv/bge.S b/isa/rv64uv/bge.S
index 06d15de..165dbe8 100644
--- a/isa/rv64uv/bge.S
+++ b/isa/rv64uv/bge.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------
diff --git a/isa/rv64uv/bgeu.S b/isa/rv64uv/bgeu.S
index 5f54670..551456f 100644
--- a/isa/rv64uv/bgeu.S
+++ b/isa/rv64uv/bgeu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------
diff --git a/isa/rv64uv/blt.S b/isa/rv64uv/blt.S
index 913c55f..787d64d 100644
--- a/isa/rv64uv/blt.S
+++ b/isa/rv64uv/blt.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------
diff --git a/isa/rv64uv/bltu.S b/isa/rv64uv/bltu.S
index 5629791..c187efd 100644
--- a/isa/rv64uv/bltu.S
+++ b/isa/rv64uv/bltu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------
diff --git a/isa/rv64uv/bne.S b/isa/rv64uv/bne.S
index a6b2347..ab31b6d 100644
--- a/isa/rv64uv/bne.S
+++ b/isa/rv64uv/bne.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------
diff --git a/isa/rv64uv/fcvt.S b/isa/rv64uv/fcvt.S
index 180712f..227a154 100644
--- a/isa/rv64uv/fcvt.S
+++ b/isa/rv64uv/fcvt.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,32
diff --git a/isa/rv64uv/fence.S b/isa/rv64uv/fence.S
index 7e9b90e..5e8072c 100644
--- a/isa/rv64uv/fence.S
+++ b/isa/rv64uv/fence.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   # make sure these don't choke at the beginning
diff --git a/isa/rv64uv/fld.S b/isa/rv64uv/fld.S
index c86fbc9..d41e761 100644
--- a/isa/rv64uv/fld.S
+++ b/isa/rv64uv/fld.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,1
diff --git a/isa/rv64uv/flw.S b/isa/rv64uv/flw.S
index d9e6da4..7e940f6 100644
--- a/isa/rv64uv/flw.S
+++ b/isa/rv64uv/flw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,1
diff --git a/isa/rv64uv/fma.S b/isa/rv64uv/fma.S
index ab6f91c..e875c61 100644
--- a/isa/rv64uv/fma.S
+++ b/isa/rv64uv/fma.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64UF
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 3,2
diff --git a/isa/rv64uv/fmovn.S b/isa/rv64uv/fmovn.S
index a943326..47a6a39 100644
--- a/isa/rv64uv/fmovn.S
+++ b/isa/rv64uv/fmovn.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,2
diff --git a/isa/rv64uv/fmovz.S b/isa/rv64uv/fmovz.S
index 9142cf0..f3e09b6 100644
--- a/isa/rv64uv/fmovz.S
+++ b/isa/rv64uv/fmovz.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,2
diff --git a/isa/rv64uv/fsd.S b/isa/rv64uv/fsd.S
index b6b60fe..f220679 100644
--- a/isa/rv64uv/fsd.S
+++ b/isa/rv64uv/fsd.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,1
diff --git a/isa/rv64uv/fsw.S b/isa/rv64uv/fsw.S
index eaafeff..71c1d2f 100644
--- a/isa/rv64uv/fsw.S
+++ b/isa/rv64uv/fsw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,1
diff --git a/isa/rv64uv/imul.S b/isa/rv64uv/imul.S
index 0925e59..1b3a2dd 100644
--- a/isa/rv64uv/imul.S
+++ b/isa/rv64uv/imul.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 3,0
diff --git a/isa/rv64uv/lb.S b/isa/rv64uv/lb.S
index 7e20b65..46ca639 100644
--- a/isa/rv64uv/lb.S
+++ b/isa/rv64uv/lb.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/lbu.S b/isa/rv64uv/lbu.S
index 166f40e..47c2261 100644
--- a/isa/rv64uv/lbu.S
+++ b/isa/rv64uv/lbu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/ld.S b/isa/rv64uv/ld.S
index a2f6b89..354ee38 100644
--- a/isa/rv64uv/ld.S
+++ b/isa/rv64uv/ld.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/lh.S b/isa/rv64uv/lh.S
index 910ffd3..e4ff176 100644
--- a/isa/rv64uv/lh.S
+++ b/isa/rv64uv/lh.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/lhu.S b/isa/rv64uv/lhu.S
index 7d4fb5a..dadf99b 100644
--- a/isa/rv64uv/lhu.S
+++ b/isa/rv64uv/lhu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/lw.S b/isa/rv64uv/lw.S
index 8b15636..182dc89 100644
--- a/isa/rv64uv/lw.S
+++ b/isa/rv64uv/lw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/lwu.S b/isa/rv64uv/lwu.S
index 6cbb302..d6df839 100644
--- a/isa/rv64uv/lwu.S
+++ b/isa/rv64uv/lwu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/movn.S b/isa/rv64uv/movn.S
index 84bb27e..df9b838 100644
--- a/isa/rv64uv/movn.S
+++ b/isa/rv64uv/movn.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/movz.S b/isa/rv64uv/movz.S
index 9332811..374b271 100644
--- a/isa/rv64uv/movz.S
+++ b/isa/rv64uv/movz.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
diff --git a/isa/rv64uv/sb.S b/isa/rv64uv/sb.S
index 9155de9..5cbe76a 100644
--- a/isa/rv64uv/sb.S
+++ b/isa/rv64uv/sb.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/sd.S b/isa/rv64uv/sd.S
index 67b336c..053c401 100644
--- a/isa/rv64uv/sd.S
+++ b/isa/rv64uv/sd.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/sh.S b/isa/rv64uv/sh.S
index e35a77b..25bb258 100644
--- a/isa/rv64uv/sh.S
+++ b/isa/rv64uv/sh.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/sw.S b/isa/rv64uv/sw.S
index 6f883ff..8f1599b 100644
--- a/isa/rv64uv/sw.S
+++ b/isa/rv64uv/sw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
diff --git a/isa/rv64uv/utidx.S b/isa/rv64uv/utidx.S
index 7de7a20..0439115 100644
--- a/isa/rv64uv/utidx.S
+++ b/isa/rv64uv/utidx.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 2,0
diff --git a/isa/rv64uv/vfmvv.S b/isa/rv64uv/vfmvv.S
index 6154620..68e085e 100644
--- a/isa/rv64uv/vfmvv.S
+++ b/isa/rv64uv/vfmvv.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 2,2
diff --git a/isa/rv64uv/vmsv.S b/isa/rv64uv/vmsv.S
index b66288c..d469e59 100644
--- a/isa/rv64uv/vmsv.S
+++ b/isa/rv64uv/vmsv.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 3,0
diff --git a/isa/rv64uv/vmvv.S b/isa/rv64uv/vmvv.S
index 3b316b9..be1adb3 100644
--- a/isa/rv64uv/vmvv.S
+++ b/isa/rv64uv/vmvv.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 3,0
diff --git a/isa/rv64uv/vsetcfg.S b/isa/rv64uv/vsetcfg.S
index 8962782..f0f532e 100644
--- a/isa/rv64uv/vsetcfg.S
+++ b/isa/rv64uv/vsetcfg.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------
diff --git a/isa/rv64uv/vsetcfgi.S b/isa/rv64uv/vsetcfgi.S
index 56e30ff..18f3294 100644
--- a/isa/rv64uv/vsetcfgi.S
+++ b/isa/rv64uv/vsetcfgi.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------
diff --git a/isa/rv64uv/vsetvl.S b/isa/rv64uv/vsetvl.S
index 019439a..1897ebf 100644
--- a/isa/rv64uv/vsetvl.S
+++ b/isa/rv64uv/vsetvl.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------
diff --git a/isa/rv64uv/vvadd_branch.S b/isa/rv64uv/vvadd_branch.S
index 539ba92..5f9f3a4 100644
--- a/isa/rv64uv/vvadd_branch.S
+++ b/isa/rv64uv/vvadd_branch.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0
diff --git a/isa/rv64uv/vvadd_d.S b/isa/rv64uv/vvadd_d.S
index bf032fa..8875b95 100644
--- a/isa/rv64uv/vvadd_d.S
+++ b/isa/rv64uv/vvadd_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0
diff --git a/isa/rv64uv/vvadd_fd.S b/isa/rv64uv/vvadd_fd.S
index 7b2ce98..2912b70 100644
--- a/isa/rv64uv/vvadd_fd.S
+++ b/isa/rv64uv/vvadd_fd.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,32
diff --git a/isa/rv64uv/vvadd_fw.S b/isa/rv64uv/vvadd_fw.S
index 0b3138b..571c457 100644
--- a/isa/rv64uv/vvadd_fw.S
+++ b/isa/rv64uv/vvadd_fw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,32
diff --git a/isa/rv64uv/vvadd_w.S b/isa/rv64uv/vvadd_w.S
index 6e194b2..f81c42e 100644
--- a/isa/rv64uv/vvadd_w.S
+++ b/isa/rv64uv/vvadd_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0
diff --git a/isa/rv64uv/vvmul_d.S b/isa/rv64uv/vvmul_d.S
index 335fe3b..a6a9d4a 100644
--- a/isa/rv64uv/vvmul_d.S
+++ b/isa/rv64uv/vvmul_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0
diff --git a/isa/rv64uv/wakeup.S b/isa/rv64uv/wakeup.S
index 9fadeba..008423a 100644
--- a/isa/rv64uv/wakeup.S
+++ b/isa/rv64uv/wakeup.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   # make sure these don't choke at the beginning