diff options
| author | Andrew Waterman <andrew@sifive.com> | 2017-04-07 16:19:47 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-04-07 16:19:47 -0700 |
| commit | fd4769977e79953fcf0decb68475d34f1d4c2d2a (patch) | |
| tree | 4a175fe9fad1d13b1fb615508c49a6b6757435d2 /isa | |
| parent | ce4b19d7b75cd024b81c09fb98c99bf4298ae7ad (diff) | |
| download | riscv-tests-fd4769977e79953fcf0decb68475d34f1d4c2d2a.zip riscv-tests-fd4769977e79953fcf0decb68475d34f1d4c2d2a.tar.gz riscv-tests-fd4769977e79953fcf0decb68475d34f1d4c2d2a.tar.bz2 | |
Remove defunct IPI tests
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv32mi/Makefrag | 3 | ||||
| -rw-r--r-- | isa/rv32mi/ipi.S | 7 | ||||
| -rw-r--r-- | isa/rv64mi/Makefrag | 3 | ||||
| -rw-r--r-- | isa/rv64mi/ipi.S | 49 |
4 files changed, 0 insertions, 62 deletions
diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag index a726244..5ee7edc 100644 --- a/isa/rv32mi/Makefrag +++ b/isa/rv32mi/Makefrag @@ -13,9 +13,6 @@ rv32mi_sc_tests = \ sbreak \ shamt \ -rv32mi_mc_tests = \ - ipi \ - rv32mi_p_tests = $(addprefix rv32mi-p-, $(rv32mi_sc_tests)) spike32_tests += $(rv32mi_p_tests) diff --git a/isa/rv32mi/ipi.S b/isa/rv32mi/ipi.S deleted file mode 100644 index c39fc29..0000000 --- a/isa/rv32mi/ipi.S +++ /dev/null @@ -1,7 +0,0 @@ -# See LICENSE for license details. - -#include "riscv_test.h" -#undef RVTEST_RV64M -#define RVTEST_RV64M RVTEST_RV32M - -#include "../rv64mi/ipi.S" diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag index e4fa426..fb38e5f 100644 --- a/isa/rv64mi/Makefrag +++ b/isa/rv64mi/Makefrag @@ -12,9 +12,6 @@ rv64mi_sc_tests = \ scall \ sbreak \ -rv64mi_mc_tests = \ - ipi \ - rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests)) spike_tests += $(rv64mi_p_tests) diff --git a/isa/rv64mi/ipi.S b/isa/rv64mi/ipi.S deleted file mode 100644 index 7178310..0000000 --- a/isa/rv64mi/ipi.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ipi.S -#----------------------------------------------------------------------------- -# -# Test interprocessor interrupts. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64M -RVTEST_CODE_BEGIN - - # enable interrupts - csrs mstatus, MSTATUS_MIE - csrs mie, MIP_MSIP - - # get a unique core id - la a0, coreid - li a1, 1 - amoadd.w a2, a1, (a0) - - # for now, only run this on core 0 - 1:li a3, 1 - bgeu a2, a3, 1b - - # send a self-IPI - csrwi mipi, 1 - 1: j 1b - -mtvec_handler: - bnez a2, fail - RVTEST_PASS - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -coreid: .word 0 -foo: .word 0 - -RVTEST_DATA_END |