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| author | Andrew Waterman <aswaterman@gmail.com> | 2017-11-20 11:59:28 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-11-20 11:59:28 -0800 |
| commit | ea53b10a55e523672340af4bf5ae710e3e314a32 (patch) | |
| tree | b5bcb52ce5fb6d7d55415f000b21fc782c4c1f7f /isa | |
| parent | 669ac25d0db3888f2c41e3f50344d728be29a701 (diff) | |
| download | riscv-tests-ea53b10a55e523672340af4bf5ae710e3e314a32.zip riscv-tests-ea53b10a55e523672340af4bf5ae710e3e314a32.tar.gz riscv-tests-ea53b10a55e523672340af4bf5ae710e3e314a32.tar.bz2 | |
Check mtval in rv64mi-p-illegal (#104)
Closes #103
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64mi/illegal.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S index 3bb7961..d825c44 100644 --- a/isa/rv64mi/illegal.S +++ b/isa/rv64mi/illegal.S @@ -130,6 +130,17 @@ synchronous_exception: csrr t0, mcause bne t0, t1, fail csrr t0, mepc + + # Make sure mtval contains either 0 or the instruction word. + csrr t2, mbadaddr + beqz t2, 1f + lhu t3, 0(t0) + lhu t4, 2(t0) + slli t4, t4, 16 + or t3, t3, t4 + bne t2, t3, fail +1: + la t1, bad2 beq t0, t1, 2f la t1, bad3 |