diff options
| author | Srivatsa Yogendra <36861801+srivatsa611y@users.noreply.github.com> | 2018-08-21 13:14:07 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-08-21 13:14:07 -0700 |
| commit | 5b4eb413c2620d4f29af1a8954871a74be8dee25 (patch) | |
| tree | db3c68215914a0e3e31f6aa99dde206e5dfa1761 /isa | |
| parent | eebc9c3dd9c96c461ff3304b1cdfb1f2a0f35b41 (diff) | |
| download | riscv-tests-5b4eb413c2620d4f29af1a8954871a74be8dee25.zip riscv-tests-5b4eb413c2620d4f29af1a8954871a74be8dee25.tar.gz riscv-tests-5b4eb413c2620d4f29af1a8954871a74be8dee25.tar.bz2 | |
Changing the register mstatus is read into (#152)
The mstatus reading overwrites the expected user mode cause value.
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64si/scall.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S index 0579806..82f202a 100644 --- a/isa/rv64si/scall.S +++ b/isa/rv64si/scall.S @@ -34,8 +34,8 @@ RVTEST_CODE_BEGIN # Otherwise, if in S mode, then U mode must exist and we don't need to check. li t0, MSTATUS_MPP csrc mstatus, t0 - csrr t1, mstatus - and t0, t0, t1 + csrr t2, mstatus + and t0, t0, t2 beqz t0, 1f # If U mode doesn't exist, mcause should indicate ECALL from M mode. |