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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-05 17:24:07 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-05 17:24:07 -0800 |
| commit | 8d64e7a32c62d2239007fb6dcc274751c629b7f8 (patch) | |
| tree | b2aa7b01df4e54aa8b5ab5289f8361ab28af2e75 /isa/rv64uv/fsw.S | |
| parent | 532db85c68d3517ed46f2d9203a3e72db5c8dec3 (diff) | |
| download | riscv-tests-8d64e7a32c62d2239007fb6dcc274751c629b7f8.zip riscv-tests-8d64e7a32c62d2239007fb6dcc274751c629b7f8.tar.gz riscv-tests-8d64e7a32c62d2239007fb6dcc274751c629b7f8.tar.bz2 | |
correctly set SR_EA bit for all vector physical tests
Diffstat (limited to 'isa/rv64uv/fsw.S')
| -rw-r--r-- | isa/rv64uv/fsw.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/isa/rv64uv/fsw.S b/isa/rv64uv/fsw.S index eaafeff..71c1d2f 100644 --- a/isa/rv64uv/fsw.S +++ b/isa/rv64uv/fsw.S @@ -8,7 +8,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UV RVTEST_CODE_BEGIN vsetcfg 4,1 |