initial commit

10 files changed, 970 insertions, 0 deletions

diff --git a/isa/rv64sv/Makefile b/isa/rv64sv/Makefile
new file mode 100644
index 0000000..670f8d9
--- /dev/null
+++ b/isa/rv64sv/Makefile
@@ -0,0 +1,101 @@
+#=======================================================================
+# Makefile for riscv-tests
+#-----------------------------------------------------------------------
+
+default: all
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+rv64sv_sc_tests = \
+	illegal_tvec_cmd illegal_tvec_regid \
+	illegal_vt_inst illegal_vt_regid \
+	ma_utld ma_utsd ma_vld ma_vsd \
+	ma_vt_inst \
+
+rv64sv_mc_tests = \
+
+rv64sv_sc_vec_tests = \
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_GCC = riscv-gcc
+RISCV_GCC_OPTS = -nostdlib -nostartfiles
+RISCV_OBJDUMP = riscv-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.data --section=.bss
+RISCV_SIM = riscv-isa-run
+
+#------------------------------------------------------------
+# Build assembly tests
+
+%.hex: %
+	elf2hex 16 16384 $< > $@
+
+%.dump: %
+	$(RISCV_OBJDUMP) $< > $@
+
+%.out: %
+	$(RISCV_SIM) $< 2> $@
+
+rv64sv_p_tests_bin = $(addprefix rv64sv-p-, $(rv64sv_sc_tests))
+rv64sv_p_tests_dump = $(addsuffix .dump, $(rv64sv_p_tests_bin))
+rv64sv_p_tests_hex = $(addsuffix .hex, $(rv64sv_p_tests_bin))
+rv64sv_p_tests_out  = $(addsuffix .out,  $(rv64sv_p_tests_bin))
+
+$(rv64sv_p_tests_bin): rv64sv-p-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/scalar -T../../env/p/link.ld $< -o $@
+
+rv64sv_pm_tests_bin = $(addprefix rv64sv-pm-, $(rv64sv_mc_tests))
+rv64sv_pm_tests_dump = $(addsuffix .dump, $(rv64sv_pm_tests_bin))
+rv64sv_pm_tests_hex = $(addsuffix .hex, $(rv64sv_pm_tests_bin))
+rv64sv_pm_tests_out  = $(addsuffix .out,  $(rv64sv_pm_tests_bin))
+
+$(rv64sv_pm_tests_bin): rv64sv-pm-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pm -I../macros/scalar -T../../env/pm/link.ld $< -o $@
+
+rv64sv_p_vec_tests_bin = $(addprefix rv64sv-p-vec-, $(rv64sv_sc_vec_tests))
+rv64sv_p_vec_tests_dump = $(addsuffix .dump, $(rv64sv_p_vec_tests_bin))
+rv64sv_p_vec_tests_hex = $(addsuffix .hex, $(rv64sv_p_vec_tests_bin))
+rv64sv_p_vec_tests_out  = $(addsuffix .out,  $(rv64sv_p_vec_tests_bin))
+
+$(rv64sv_p_vec_tests_bin): rv64sv-p-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/vector -T../../env/p/link.ld $< -o $@
+
+rv64sv_pt_vec_tests_bin = $(addprefix rv64sv-pt-vec-, $(rv64sv_sc_vec_tests))
+rv64sv_pt_vec_tests_dump = $(addsuffix .dump, $(rv64sv_pt_vec_tests_bin))
+rv64sv_pt_vec_tests_hex = $(addsuffix .hex, $(rv64sv_pt_vec_tests_bin))
+rv64sv_pt_vec_tests_out  = $(addsuffix .out,  $(rv64sv_pt_vec_tests_bin))
+
+$(rv64sv_pt_vec_tests_bin): rv64sv-pt-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pt -I../macros/vector -T../../env/pt/link.ld $< -o $@
+
+riscv-: \
+	$(rv64sv_p_tests_dump) $(rv64sv_p_tests_hex) \
+	$(rv64sv_pm_tests_dump) $(rv64sv_pm_tests_hex) \
+	$(rv64sv_p_vec_tests_dump) $(rv64sv_p_vec_tests_hex) \
+	$(rv64sv_pt_vec_tests_dump) $(rv64sv_pt_vec_tests_hex) \
+
+out =
+
+run: $(out)
+	echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
+	       $(out); echo;
+
+junk += \
+  $(rv64sv_p_tests_bin) $(rv64sv_p_tests_dump) $(rv64sv_p_tests_hex) $(rv64sv_p_tests_out) \
+  $(rv64sv_pm_tests_bin) $(rv64sv_pm_tests_dump) $(rv64sv_pm_tests_hex) $(rv64sv_pm_tests_out) \
+  $(rv64sv_p_vec_tests_bin) $(rv64sv_p_vec_tests_dump) $(rv64sv_p_vec_tests_hex) $(rv64sv_p_vec_tests_out) \
+  $(rv64sv_pt_vec_tests_bin) $(rv64sv_pt_vec_tests_dump) $(rv64sv_pt_vec_tests_hex) $(rv64sv_pt_vec_tests_out) \
+
+#------------------------------------------------------------
+# Default
+
+all: riscv-
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(junk)
diff --git a/isa/rv64sv/illegal_tvec_cmd.S b/isa/rv64sv/illegal_tvec_cmd.S
new file mode 100644
index 0000000..d6d8d38
--- /dev/null
+++ b/isa/rv64sv/illegal_tvec_cmd.S
@@ -0,0 +1,112 @@
+#*****************************************************************************
+# illegal_tvec_cmd.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal tvec command trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3, dest+1
+  vmsv vx1, a3
+  addi a3, x0, 0x1
+  sll a3, a3, 12
+  venqcmd a3, x0
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  fence.v.l
+
+vtcode1:
+  lw x2, 0(x1)
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,27
+  bne a3,a4,fail
+
+  # check vec irq aux
+  mfpcr a3,cr2
+  addi a4, x0, 0x1
+  sll a4, a4, 12
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S
new file mode 100644
index 0000000..4f48f8f
--- /dev/null
+++ b/isa/rv64sv/illegal_tvec_regid.S
@@ -0,0 +1,51 @@
+#*****************************************************************************
+# illegal_tvec_regid.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal tvec regid trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a0,cr0
+  li a1,1
+  slli a2,a1,8
+  or a0,a0,a1 # enable traps
+  mtpcr a0,cr0
+
+  TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2, 0x931c7)
+  TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2, 0x831c7)
+
+  TEST_ILLEGAL_TVEC_REGID(4, 5, 5, vfsd, vf7, a2, 0x9b9e7)
+  TEST_ILLEGAL_TVEC_REGID(5, 5, 5, vfld, vf7, a2, 0x8b9e7)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
new file mode 100644
index 0000000..d749104
--- /dev/null
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -0,0 +1,112 @@
+#*****************************************************************************
+# illegal_vt_inst.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal vt instruction trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  fence.v.l
+
+vtcode1:
+  add x2,x2,x3
+illegal:
+  .word 0x0
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,26
+  bne a3,a4,fail
+
+  # check badvaddr
+  mfpcr a3,cr2
+  la a4,illegal
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
new file mode 100644
index 0000000..8baa918
--- /dev/null
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -0,0 +1,53 @@
+#*****************************************************************************
+# xcpt_illegal_vt_regid.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal vt regid trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a0,cr0
+  li a1,1
+  slli a2,a1,8
+  or a0,a0,a1 # enable traps
+  mtpcr a0,cr0
+
+  TEST_ILLEGAL_VT_REGID(2, 5, 5, add, x7, x1, x2)
+  TEST_ILLEGAL_VT_REGID(3, 5, 5, add, x1, x7, x2)
+  TEST_ILLEGAL_VT_REGID(4, 5, 5, add, x1, x2, x7)
+
+  TEST_ILLEGAL_VT_REGID(5, 5, 5, fadd.d, f7, f1, f2)
+  TEST_ILLEGAL_VT_REGID(6, 5, 5, fadd.d, f1, f7, f2)
+  TEST_ILLEGAL_VT_REGID(7, 5, 5, fadd.d, f1, f2, f7)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
new file mode 100644
index 0000000..a71c4a1
--- /dev/null
+++ b/isa/rv64sv/ma_utld.S
@@ -0,0 +1,108 @@
+#*****************************************************************************
+# ma_utld.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned ut ld trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3, dest+1
+  vmsv vx1, a3
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  fence.v.l
+
+vtcode1:
+  lw x2, 0(x1)
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,28
+  bne a3,a4,fail
+
+  # check vec irq aux
+  mfpcr a3,cr2
+  la a4,dest+1
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
new file mode 100644
index 0000000..6bdfcd5
--- /dev/null
+++ b/isa/rv64sv/ma_utsd.S
@@ -0,0 +1,110 @@
+#*****************************************************************************
+# ma_utsd.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned ut sd trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3, dest+1
+  vmsv vx1, a3
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a3, dest+1
+  vsd vx1, a3
+  fence.v.l
+
+vtcode1:
+  sw x2, 0(x1)
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,29
+  bne a3,a4,fail
+
+  # check vec irq aux
+  mfpcr a3,cr2
+  la a4, dest+1
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
new file mode 100644
index 0000000..ef862c4
--- /dev/null
+++ b/isa/rv64sv/ma_vld.S
@@ -0,0 +1,109 @@
+#*****************************************************************************
+# ma_vld.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned vector ld trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3, dest+1
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  fence.v.l
+
+vtcode1:
+  add x2,x2,x3
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,28
+  bne a3,a4,fail
+
+  # check vec irq aux
+  mfpcr a3,cr2
+  la a4,dest+1
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
new file mode 100644
index 0000000..b82eb98
--- /dev/null
+++ b/isa/rv64sv/ma_vsd.S
@@ -0,0 +1,112 @@
+#*****************************************************************************
+# ma_vsd.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned vector sd trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3, src1
+  la a4, src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a3, dest+1
+  vsd vx1, a3
+  fence.v.l
+
+vtcode1:
+  add x2,x2,x3
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,29
+  bne a3,a4,fail
+
+  # check vec irq aux
+  mfpcr a3,cr2
+  la a4,dest+1
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
new file mode 100644
index 0000000..c8b7acb
--- /dev/null
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -0,0 +1,102 @@
+#*****************************************************************************
+# ma_vt_inst.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned vt instruction trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  lui a0,%hi(vtcode1+2)
+  vf %lo(vtcode1+2)(a0)
+1:      j 1b
+
+vtcode1:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,24
+  bne a3,a4,fail
+
+  # check badvaddr
+  mfpcr a3,cr2
+  la a4,vtcode1+2
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END