revamp hwacha tests

7 files changed, 41 insertions, 27 deletions

diff --git a/isa/rv64sv/illegal_tvec_cmd.S b/isa/rv64sv/illegal_tvec_cmd.S
index d6d8d38..8943d86 100644
--- a/isa/rv64sv/illegal_tvec_cmd.S
+++ b/isa/rv64sv/illegal_tvec_cmd.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vmsv vx1, a3
@@ -30,7 +31,7 @@ RVTEST_CODE_BEGIN
   venqcmd a3, x0
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   lw x2, 0(x1)
@@ -57,8 +58,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -68,7 +70,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5
diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index d749104..d0e5574 100644
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -29,7 +30,7 @@ RVTEST_CODE_BEGIN
   vld vx3,a4
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   add x2,x2,x3
@@ -57,8 +58,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -68,7 +70,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5
diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index a71c4a1..7b5db04 100644
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -20,14 +20,15 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vmsv vx1, a3
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   lw x2, 0(x1)
@@ -53,8 +54,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -64,7 +66,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5
diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 6bdfcd5..3b9e094 100644
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vmsv vx1, a3
@@ -29,7 +30,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode1)(a0)
   la a3, dest+1
   vsd vx1, a3
-  fence.v.l
+  fence
 
 vtcode1:
   sw x2, 0(x1)
@@ -55,8 +56,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -66,7 +68,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5
diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index ef862c4..bcf4b5a 100644
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -20,15 +20,16 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vld vx2,a3
   vld vx3,a4
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   add x2,x2,x3
@@ -54,8 +55,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -65,7 +67,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5
diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index b82eb98..6822250 100644
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, src1
   la a4, src2
@@ -31,7 +32,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode1)(a0)
   la a3, dest+1
   vsd vx1, a3
-  fence.v.l
+  fence
 
 vtcode1:
   add x2,x2,x3
@@ -57,8 +58,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -68,7 +70,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5
diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index c8b7acb..185924c 100644
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   lui a0,%hi(vtcode1+2)
   vf %lo(vtcode1+2)(a0)
@@ -47,8 +48,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -58,7 +60,7 @@ handler:
   vf %lo(vtcode1)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5