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author | Tim Newsome <tim@sifive.com> | 2018-04-02 14:56:45 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2018-04-02 14:56:45 -0700 |
commit | 4ab18e0f8e6381f0a16e8b812d4ee202e9465192 (patch) | |
tree | ae14069135c153bc05d74252466ae44cee628b5f /debug/targets/RISC-V/spike-rtos.cfg | |
parent | 45380af7d42ee3302fc229030694f8ea4506d79f (diff) | |
download | riscv-tests-4ab18e0f8e6381f0a16e8b812d4ee202e9465192.zip riscv-tests-4ab18e0f8e6381f0a16e8b812d4ee202e9465192.tar.gz riscv-tests-4ab18e0f8e6381f0a16e8b812d4ee202e9465192.tar.bz2 |
Use `gdb_report_register_access_error enable`
Diffstat (limited to 'debug/targets/RISC-V/spike-rtos.cfg')
-rw-r--r-- | debug/targets/RISC-V/spike-rtos.cfg | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg index 159a70f..d8bd27e 100644 --- a/debug/targets/RISC-V/spike-rtos.cfg +++ b/debug/targets/RISC-V/spike-rtos.cfg @@ -12,6 +12,7 @@ set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv gdb_report_data_abort enable +gdb_report_register_access_error enable # Expose an unimplemented CSR so we can test non-existent register access # behavior. |