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| author | Tim Newsome <tim@sifive.com> | 2018-01-08 12:36:49 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-01-08 12:36:49 -0800 |
| commit | 6d97e25f4da3e92dee131b1836184836ef280b26 (patch) | |
| tree | 678cb21b5d8a231746696ed3a4bb3bdf2381ab31 /debug/gdbserver.py | |
| parent | c2e2e06836b597d983c98f33a7ea38e8e4889935 (diff) | |
| download | riscv-tests-6d97e25f4da3e92dee131b1836184836ef280b26.zip riscv-tests-6d97e25f4da3e92dee131b1836184836ef280b26.tar.gz riscv-tests-6d97e25f4da3e92dee131b1836184836ef280b26.tar.bz2 | |
Deal with gdb reporting pmpcfg0 not existing.
It's an optional register.
Diffstat (limited to 'debug/gdbserver.py')
| -rwxr-xr-x | debug/gdbserver.py | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index bf27950..8c500bc 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -855,9 +855,13 @@ class PrivRw(PrivTest): """Test reading/writing priv.""" # Disable physical memory protection by allowing U mode access to all # memory. - self.gdb.p("$pmpcfg0=0xf") # TOR, R, W, X - self.gdb.p("$pmpaddr0=0x%x" % - ((self.hart.ram + self.hart.ram_size) >> 2)) + try: + self.gdb.p("$pmpcfg0=0xf") # TOR, R, W, X + self.gdb.p("$pmpaddr0=0x%x" % + ((self.hart.ram + self.hart.ram_size) >> 2)) + except testlib.CouldNotFetch: + # PMP registers are optional + pass # Leave the PC at _start, where the first 4 instructions should be # legal in any mode. |