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| author | Tim Newsome <tim@sifive.com> | 2017-11-19 20:54:14 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-11-19 20:54:14 -0800 |
| commit | 8e0f6a0b1a33d35f2248628af7333ede093341d0 (patch) | |
| tree | 7378eb90594b13f19c834133fadb307238941e21 /debug/gdbserver.py | |
| parent | 3714cacfdd8f1a20f58e7e217e1d737cecdf5340 (diff) | |
| download | riscv-tests-8e0f6a0b1a33d35f2248628af7333ede093341d0.zip riscv-tests-8e0f6a0b1a33d35f2248628af7333ede093341d0.tar.gz riscv-tests-8e0f6a0b1a33d35f2248628af7333ede093341d0.tar.bz2 | |
Make pylint happy.
Diffstat (limited to 'debug/gdbserver.py')
| -rwxr-xr-x | debug/gdbserver.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 09938d3..49e42e7 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -817,7 +817,8 @@ class PrivRw(PrivTest): # Disable physical memory protection by allowing U mode access to all # memory. self.gdb.p("$pmpcfg0=0xf") # TOR, R, W, X - self.gdb.p("$pmpaddr0=0x%x" % ((self.hart.ram + self.hart.ram_size) >> 2)) + self.gdb.p("$pmpaddr0=0x%x" % + ((self.hart.ram + self.hart.ram_size) >> 2)) # Leave the PC at _start, where the first 4 instructions should be # legal in any mode. |