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| author | Tim Newsome <tim@sifive.com> | 2017-09-01 12:03:40 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-09-01 12:03:40 -0700 |
| commit | 5acbf6414ddaa6552ead5099868897a161bd945f (patch) | |
| tree | 9a778753f9ea3c48fc89c0732aeaa3baf56ea0ca | |
| parent | ea039ea3cec43fefa1df96339bea93a5dcb06d5a (diff) | |
| download | riscv-tests-5acbf6414ddaa6552ead5099868897a161bd945f.zip riscv-tests-5acbf6414ddaa6552ead5099868897a161bd945f.tar.gz riscv-tests-5acbf6414ddaa6552ead5099868897a161bd945f.tar.bz2 | |
Use 32-bit link script for 32-bit target.
| -rw-r--r-- | debug/targets/RISC-V/spike32.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index fc7d598..665d7e9 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -7,7 +7,7 @@ class spike32_hart(targets.Hart): ram_size = 0x10000000 instruction_hardware_breakpoint_count = 4 reset_vector = 0x1000 - link_script_path = "spike64.lds" + link_script_path = "spike32.lds" class spike32(targets.Target): harts = [spike32_hart()] |