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| author | Tim Newsome <tim@sifive.com> | 2022-05-16 09:14:43 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-16 09:14:43 -0700 |
| commit | fd6e7ed1707b3449f9673fa6b3bc1e422af4669b (patch) | |
| tree | f4f015182c0a816edaa9d62261ba05824d878d11 | |
| parent | 4f37484c91fe97c9cca7e0ca6cfe98c63c365a12 (diff) | |
| download | riscv-tests-fd6e7ed1707b3449f9673fa6b3bc1e422af4669b.zip riscv-tests-fd6e7ed1707b3449f9673fa6b3bc1e422af4669b.tar.gz riscv-tests-fd6e7ed1707b3449f9673fa6b3bc1e422af4669b.tar.bz2 | |
V implies FD now. (#382)
Adjust test to work with that.
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-hwthread.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py index e84391a..d54136d 100644 --- a/debug/targets/RISC-V/spike32-2-hwthread.py +++ b/debug/targets/RISC-V/spike32-2-hwthread.py @@ -4,13 +4,13 @@ import testlib import spike32 # pylint: disable=import-error class spike32_2(targets.Target): - harts = [spike32.spike32_hart(misa=0x40341101), - spike32.spike32_hart(misa=0x40341101)] + harts = [spike32.spike32_hart(misa=0x40341129), + spike32.spike32_hart(misa=0x40341129)] openocd_config_path = "spike-2-hwthread.cfg" timeout_sec = 5 implements_custom_test = True support_memory_sampling = False # not supported without sba def create(self): - return testlib.Spike(self, isa="RV32IMAV", support_hasel=True, + return testlib.Spike(self, isa="RV32IMAFDV", support_hasel=True, support_haltgroups=False) |