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| author | Tim Newsome <tim@sifive.com> | 2021-11-12 11:29:32 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-11-12 11:29:32 -0800 |
| commit | d649367a1386609da3d10e9e6d388f98781dd35f (patch) | |
| tree | be56ddeafc6fa37d1c21bf9d9af4b427baf04460 | |
| parent | 515d185db118a54e920514c6fc7783d95b530d4c (diff) | |
| download | riscv-tests-d649367a1386609da3d10e9e6d388f98781dd35f.zip riscv-tests-d649367a1386609da3d10e9e6d388f98781dd35f.tar.gz riscv-tests-d649367a1386609da3d10e9e6d388f98781dd35f.tar.bz2 | |
Set `riscv resume_order reversed`. (#363)
The tests don't confirm that the order actually changes, but at least
the code that does the work now is executed during the tests.
| -rw-r--r-- | debug/targets/RISC-V/spike-2-hwthread.cfg | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike-2-hwthread.cfg b/debug/targets/RISC-V/spike-2-hwthread.cfg index c378a45..dc60ced 100644 --- a/debug/targets/RISC-V/spike-2-hwthread.cfg +++ b/debug/targets/RISC-V/spike-2-hwthread.cfg @@ -25,6 +25,8 @@ foreach t [target names] { riscv expose_custom 1,12345-12348 } +riscv resume_order reversed + init set challenge [riscv authdata_read] |