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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-02-28 23:47:09 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-03 11:03:59 -0800 |
| commit | 6906f6f470765b8165735ed06f864e00e8d9d5ec (patch) | |
| tree | 9f51fe393dd51caedcd6b9082ef6c114ceee540a | |
| parent | 9fc686ae1488a596d0bed561a750396911e71b01 (diff) | |
| download | riscv-tests-6906f6f470765b8165735ed06f864e00e8d9d5ec.zip riscv-tests-6906f6f470765b8165735ed06f864e00e8d9d5ec.tar.gz riscv-tests-6906f6f470765b8165735ed06f864e00e8d9d5ec.tar.bz2 | |
WIP on priv spec v1.9
| -rw-r--r-- | benchmarks/common/crt.S | 6 | ||||
| -rw-r--r-- | isa/Makefile | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S index 60486be..29c1d4d 100644 --- a/benchmarks/common/crt.S +++ b/benchmarks/common/crt.S @@ -64,13 +64,13 @@ _start: li x30,0 li x31,0 - li t0, MSTATUS_PRV1; csrc mstatus, t0 # run tests in user mode - li t0, MSTATUS_IE1; csrs mstatus, t0 # enable interrupts in user mode + li t0, MSTATUS_MPP; csrc mstatus, t0 # run tests in user mode + li t0, MSTATUS_MPIE; csrs mstatus, t0 # enable interrupts in user mode li t0, MSTATUS_FS; csrs mstatus, t0 # enable FPU li t0, MSTATUS_XS; csrs mstatus, t0 # enable accelerator #ifdef __riscv64 - csrr t0, mcpuid + csrr t0, misa # make sure processor supports RV64 if this was compiled for RV64 bltz t0, 1f li a0, 1234 diff --git a/isa/Makefile b/isa/Makefile index d5b0b76..d267812 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -18,7 +18,7 @@ default: all # Build rules #-------------------------------------------------------------------- -RISCV_PREFIX ?= riscv64-unknown-elf- +RISCV_PREFIX ?= riscv64-unknown-linux-gnu- RISCV_GCC ?= $(RISCV_PREFIX)gcc ENTROPY ?= -DENTROPY=$(shell echo $$$$) RISCV_GCC_OPTS ?= $(ENTROPY) -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles |