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| author | Tim Newsome <tim@sifive.com> | 2017-02-17 09:45:53 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-02-17 09:45:53 -0800 |
| commit | 7dfc16ad687186faa57368a251489e56b72b6f91 (patch) | |
| tree | 6eb2b57f12dafe2cb5bb08cd63801e295098ca1b | |
| parent | e9951fc39dff4f4030cdfaaf479b936ae37799e2 (diff) | |
| download | riscv-tests-7dfc16ad687186faa57368a251489e56b72b6f91.zip riscv-tests-7dfc16ad687186faa57368a251489e56b72b6f91.tar.gz riscv-tests-7dfc16ad687186faa57368a251489e56b72b6f91.tar.bz2 | |
Add HiFive1 target.
| -rw-r--r-- | debug/targets.py | 7 | ||||
| -rwxr-xr-x | debug/targets/HiFive1/link.lds | 34 | ||||
| -rw-r--r-- | debug/targets/HiFive1/openocd.cfg | 23 |
3 files changed, 63 insertions, 1 deletions
diff --git a/debug/targets.py b/debug/targets.py index bcebc0b..52b623c 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -92,6 +92,10 @@ class FreedomE300Target(Target): instruction_hardware_breakpoint_count = 2 openocd_config = "targets/%s/openocd.cfg" % name +class HiFive1Target(FreedomE300Target): + name = "HiFive1" + openocd_config = "targets/%s/openocd.cfg" % name + class FreedomE300SimTarget(Target): name = "freedom-e300-sim" xlen = 32 @@ -130,7 +134,8 @@ targets = [ FreedomE300Target, FreedomU500Target, FreedomE300SimTarget, - FreedomU500SimTarget] + FreedomU500SimTarget, + HiFive1Target] def add_target_options(parser): group = parser.add_mutually_exclusive_group(required=True) diff --git a/debug/targets/HiFive1/link.lds b/debug/targets/HiFive1/link.lds new file mode 100755 index 0000000..1dbb99c --- /dev/null +++ b/debug/targets/HiFive1/link.lds @@ -0,0 +1,34 @@ +OUTPUT_ARCH( "riscv" ) + +SECTIONS +{ + . = 0x80000000; + .text : + { + *(.text.entry) + *(.text) + } + + /* data segment */ + .data : { *(.data) } + + .sdata : { + _gp = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + + /* bss segment */ + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { *(.bss) } + + __malloc_start = .; + . = . + 512; + + /* End of uninitalized data segement */ + _end = .; +} diff --git a/debug/targets/HiFive1/openocd.cfg b/debug/targets/HiFive1/openocd.cfg new file mode 100644 index 0000000..d2c2879 --- /dev/null +++ b/debug/targets/HiFive1/openocd.cfg @@ -0,0 +1,23 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 + +# ... + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 + +flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset +halt +flash protect 0 64 last off |