diff options
| author | Eric Love <ericlove@s144.Millennium.Berkeley.EDU> | 2014-01-23 16:20:35 -0800 |
|---|---|---|
| committer | Eric Love <ericlove@s144.Millennium.Berkeley.EDU> | 2014-01-23 16:20:35 -0800 |
| commit | 53f417a9acfc2f2517aa93be38875d17b408ec59 (patch) | |
| tree | 7ec3a2e563cfe0985630adf704330d30d9f8d841 | |
| parent | 197479964e99ee9a0b196c9cc1a3249812477bd3 (diff) | |
| download | riscv-tests-53f417a9acfc2f2517aa93be38875d17b408ec59.zip riscv-tests-53f417a9acfc2f2517aa93be38875d17b408ec59.tar.gz riscv-tests-53f417a9acfc2f2517aa93be38875d17b408ec59.tar.bz2 | |
srl and srai
| -rw-r--r-- | isa/rv32ui/Makefrag | 4 | ||||
| -rw-r--r-- | isa/rv32ui/srai.S | 6 | ||||
| -rw-r--r-- | isa/rv32ui/srl.S | 56 |
3 files changed, 33 insertions, 33 deletions
diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag index 17b2bd8..8d6acea 100644 --- a/isa/rv32ui/Makefrag +++ b/isa/rv32ui/Makefrag @@ -19,8 +19,8 @@ rv32ui_sc_tests = \ sb sh sw \ sll slli \ slt slti \ - #sra srai \ - #srl srli \ + sra srai \ + srl #srli \ #sub \ #xor xori \ diff --git a/isa/rv32ui/srai.S b/isa/rv32ui/srai.S index 7de804c..e1adbbb 100644 --- a/isa/rv32ui/srai.S +++ b/isa/rv32ui/srai.S @@ -51,9 +51,9 @@ RVTEST_CODE_BEGIN TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffe0000, 0x80000000, 14 ); TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffff, 0x80000001, 31 ); - TEST_IMM_ZEROSRC1( 24, srai, 0, 32 ); - TEST_IMM_ZERODEST( 25, srai, 33, 50 ); - + TEST_IMM_ZEROSRC1( 24, srai, 0, 31 ); + TEST_IMM_ZERODEST( 25, srai, 33, 20 ); +# TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv32ui/srl.S b/isa/rv32ui/srl.S index 4ff5e05..8f8719d 100644 --- a/isa/rv32ui/srl.S +++ b/isa/rv32ui/srl.S @@ -15,17 +15,17 @@ RVTEST_CODE_BEGIN # Arithmetic tests #------------------------------------------------------------- - TEST_RR_OP( 2, srl, 0x80000000, 0x80000000, 0 ); - TEST_RR_OP( 3, srl, 0xc0000000, 0x80000000, 1 ); - TEST_RR_OP( 4, srl, 0xff000000, 0x80000000, 7 ); - TEST_RR_OP( 5, srl, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_OP( 6, srl, 0xffffffff, 0x80000001, 31 ); + TEST_RR_OP( 2, srl, 0xffff8000, 0xffff8000, 0 ); + TEST_RR_OP( 3, srl, 0x7fffc000, 0xffff8000, 1 ); + TEST_RR_OP( 4, srl, 0x01ffff00, 0xffff8000, 7 ); + TEST_RR_OP( 5, srl, 0x0003fffe, 0xffff8000, 14 ); + TEST_RR_OP( 6, srl, 0x0001ffff, 0xffff8001, 15 ); TEST_RR_OP( 7, srl, 0xffffffff, 0xffffffff, 0 ); - TEST_RR_OP( 8, srl, 0xffffffff, 0xffffffff, 1 ); - TEST_RR_OP( 9, srl, 0xffffffff, 0xffffffff, 7 ); - TEST_RR_OP( 10, srl, 0xffffffff, 0xffffffff, 14 ); - TEST_RR_OP( 11, srl, 0xffffffff, 0xffffffff, 31 ); + TEST_RR_OP( 8, srl, 0x7fffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, srl, 0x01ffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, srl, 0x0003ffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, srl, 0x00000001, 0xffffffff, 31 ); TEST_RR_OP( 12, srl, 0x21212121, 0x21212121, 0 ); TEST_RR_OP( 13, srl, 0x10909090, 0x21212121, 1 ); @@ -45,31 +45,31 @@ RVTEST_CODE_BEGIN # Source/Destination tests #------------------------------------------------------------- - TEST_RR_SRC1_EQ_DEST( 22, srl, 0xff000000, 0x80000000, 7 ); - TEST_RR_SRC2_EQ_DEST( 23, srl, 0xfffe0000, 0x80000000, 14 ); + TEST_RR_SRC1_EQ_DEST( 22, srl, 0x7fffc000, 0xffff8000, 1 ); + TEST_RR_SRC2_EQ_DEST( 23, srl, 0x0003fffe, 0xffff8000, 14 ); TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 ); #------------------------------------------------------------- # Bypassing tests #------------------------------------------------------------- - TEST_RR_DEST_BYPASS( 25, 0, srl, 0xff000000, 0x80000000, 7 ); - TEST_RR_DEST_BYPASS( 26, 1, srl, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_DEST_BYPASS( 27, 2, srl, 0xffffffff, 0x80000000, 31 ); - - TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0xff000000, 0x80000000, 7 ); - TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0xffffffff, 0x80000000, 31 ); - TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0xff000000, 0x80000000, 7 ); - TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0xffffffff, 0x80000000, 31 ); - - TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0xff000000, 0x80000000, 7 ); - TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0xffffffff, 0x80000000, 31 ); - TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0xff000000, 0x80000000, 7 ); - TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0xffffffff, 0x80000000, 31 ); + TEST_RR_DEST_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 ); + TEST_RR_DEST_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x7fffc000, 0xffff8000, 1 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x7fffc000, 0xffff8000, 1 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x7fffc000, 0xffff8000, 1 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x7fffc000, 0xffff8000, 1 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 ); TEST_RR_ZEROSRC1( 40, srl, 0, 15 ); TEST_RR_ZEROSRC2( 41, srl, 32, 32 ); |