Reference TESTNUM instead of x28 directly

69 files changed, 217 insertions, 217 deletions

diff --git a/env b/env
-Subproject 746361936518f56549726c3e661606e5f28a1b9
+Subproject 217bb5eef46deb0eeac7b8f11c9d36d9310feab
diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index 10680d4..dca9a92 100644
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -10,14 +10,14 @@
 test_ ## testnum: \
     code; \
     li  x29, correctval; \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     bne testreg, x29, fail;
 
 #define TEST_CASE_JUMP( testnum, testreg, correctval, code... ) \
 test_ ## testnum: \
     code; \
     li  x29, correctval; \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     beq testreg, x29, pass_ ## testnum; \
     j fail; \
 pass_ ## testnum: \
@@ -264,7 +264,7 @@ pass_ ## testnum: \
 
 #define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x1, base; \
     inst x3, offset(x1); \
@@ -278,7 +278,7 @@ test_ ## testnum: \
 
 #define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x1, base; \
     TEST_INSERT_NOPS_ ## nop_cycles \
@@ -291,7 +291,7 @@ test_ ## testnum: \
 
 #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x1, result; \
     TEST_INSERT_NOPS_ ## src1_nops \
@@ -307,7 +307,7 @@ test_ ## testnum: \
 
 #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x2, base; \
     TEST_INSERT_NOPS_ ## src1_nops \
@@ -327,28 +327,28 @@ test_ ## testnum: \
 
 #define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x1, val1; \
     inst x1, 2f; \
-    bne x0, x28, fail; \
-1:  bne x0, x28, 3f; \
+    bne x0, TESTNUM, fail; \
+1:  bne x0, TESTNUM, 3f; \
 2:  inst x1, 1b; \
-    bne x0, x28, fail; \
+    bne x0, TESTNUM, fail; \
 3:
 
 #define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x1, val1; \
     inst x1, 1f; \
-    bne x0, x28, 2f; \
-1:  bne x0, x28, fail; \
+    bne x0, TESTNUM, 2f; \
+1:  bne x0, TESTNUM, fail; \
 2:  inst x1, 1b; \
 3:
 
 #define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  li  x1, val1; \
     TEST_INSERT_NOPS_ ## nop_cycles \
@@ -359,30 +359,30 @@ test_ ## testnum: \
 
 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x1, val1; \
     li  x2, val2; \
     inst x1, x2, 2f; \
-    bne x0, x28, fail; \
-1:  bne x0, x28, 3f; \
+    bne x0, TESTNUM, fail; \
+1:  bne x0, TESTNUM, 3f; \
 2:  inst x1, x2, 1b; \
-    bne x0, x28, fail; \
+    bne x0, TESTNUM, fail; \
 3:
 
 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x1, val1; \
     li  x2, val2; \
     inst x1, x2, 1f; \
-    bne x0, x28, 2f; \
-1:  bne x0, x28, fail; \
+    bne x0, TESTNUM, 2f; \
+1:  bne x0, TESTNUM, fail; \
 2:  inst x1, x2, 1b; \
 3:
 
 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  li  x1, val1; \
     TEST_INSERT_NOPS_ ## src1_nops \
@@ -395,7 +395,7 @@ test_ ## testnum: \
 
 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  li  x2, val2; \
     TEST_INSERT_NOPS_ ## src1_nops \
@@ -412,24 +412,24 @@ test_ ## testnum: \
 
 #define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x6, 2f; \
     TEST_INSERT_NOPS_ ## nop_cycles \
     inst x6; \
-    bne x0, x28, fail; \
+    bne x0, TESTNUM, fail; \
 2:  addi  x4, x4, 1; \
     li  x5, 2; \
     bne x4, x5, 1b \
 
 #define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x6, 2f; \
     TEST_INSERT_NOPS_ ## nop_cycles \
     inst x19, x6, 0; \
-    bne x0, x28, fail; \
+    bne x0, TESTNUM, fail; \
 2:  addi  x4, x4, 1; \
     li  x5, 2; \
     bne x4, x5, 1b \
@@ -445,7 +445,7 @@ test_ ## testnum: \
 
 #define TEST_FP_OP_S_INTERNAL( testnum, result, val1, val2, val3, code... ) \
 test_ ## testnum: \
-  li  x28, testnum; \
+  li  TESTNUM, testnum; \
   la  a0, test_ ## testnum ## _data ;\
   flw f0, 0(a0); \
   flw f1, 4(a0); \
@@ -464,7 +464,7 @@ test_ ## testnum: \
 
 #define TEST_FP_OP_D_INTERNAL( testnum, result, val1, val2, val3, code... ) \
 test_ ## testnum: \
-  li  x28, testnum; \
+  li  TESTNUM, testnum; \
   la  a0, test_ ## testnum ## _data ;\
   fld f0, 0(a0); \
   fld f1, 8(a0); \
@@ -531,7 +531,7 @@ test_ ## testnum: \
 
 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
 test_ ## testnum: \
-  li  x28, testnum; \
+  li  TESTNUM, testnum; \
   la  a0, test_ ## testnum ## _data ;\
   lw  a3, 0(a0); \
   li  a0, val1; \
@@ -546,7 +546,7 @@ test_ ## testnum: \
 
 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
 test_ ## testnum: \
-  li  x28, testnum; \
+  li  TESTNUM, testnum; \
   la  a0, test_ ## testnum ## _data ;\
   ld  a3, 0(a0); \
   li  a0, val1; \
@@ -591,7 +591,7 @@ vtcode2 ## testnum: \
   stop; \
 handler ## testnum: \
   vxcptkill; \
-  li x28,2; \
+  li TESTNUM,2; \
   vxcptcause a0; \
   li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
   bne a0,a1,fail; \
@@ -613,16 +613,16 @@ handler ## testnum: \
   fence; \
   ld a1,0(a3); \
   li a2,5; \
-  li x28,2; \
+  li TESTNUM,2; \
   bne a1,a2,fail; \
   ld a1,8(a3); \
-  li x28,3; \
+  li TESTNUM,3; \
   bne a1,a2,fail; \
   ld a1,16(a3); \
-  li x28,4; \
+  li TESTNUM,4; \
   bne a1,a2,fail; \
   ld a1,24(a3); \
-  li x28,5; \
+  li TESTNUM,5; \
   bne a1,a2,fail; \
 
 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
@@ -651,7 +651,7 @@ vtcode2 ## testnum: \
   stop; \
 handler ## testnum: \
   vxcptkill; \
-  li x28,2; \
+  li TESTNUM,2; \
   vxcptcause a0; \
   li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
   bne a0,a1,fail; \
@@ -672,24 +672,24 @@ handler ## testnum: \
   fence; \
   ld a1,0(a3); \
   li a2,5; \
-  li x28,2; \
+  li TESTNUM,2; \
   bne a1,a2,fail; \
   ld a1,8(a3); \
-  li x28,3; \
+  li TESTNUM,3; \
   bne a1,a2,fail; \
   ld a1,16(a3); \
-  li x28,4; \
+  li TESTNUM,4; \
   bne a1,a2,fail; \
   ld a1,24(a3); \
-  li x28,5; \
+  li TESTNUM,5; \
   bne a1,a2,fail; \
 
 #-----------------------------------------------------------------------
-# Pass and fail code (assumes test num is in x28)
+# Pass and fail code (assumes test num is in TESTNUM)
 #-----------------------------------------------------------------------
 
 #define TEST_PASSFAIL \
-        bne x0, x28, pass; \
+        bne x0, TESTNUM, pass; \
 fail: \
         RVTEST_FAIL \
 pass: \
diff --git a/isa/macros/vector/test_macros.h b/isa/macros/vector/test_macros.h
index 932aba3..5a8f0a1 100644
--- a/isa/macros/vector/test_macros.h
+++ b/isa/macros/vector/test_macros.h
@@ -25,7 +25,7 @@ test_ ## testnum: \
   fence; \
   li a1,correctval; \
   li a2,0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   ld a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -238,7 +238,7 @@ test_ ## testnum: \
   fence; \
   lw  a1, 0(a5); \
   li a2, 0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   lw a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -278,7 +278,7 @@ test_ ## testnum: \
   fence; \
   ld  a1, 0(a5); \
   li a2, 0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   ld a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -352,7 +352,7 @@ test_ ## testnum: \
   la  a5, test_ ## testnum ## _data ;\
   lw  a1, 0(a5); \
   li a2, 0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   lw a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -385,7 +385,7 @@ test_ ## testnum: \
   la  a5, test_ ## testnum ## _data ;\
   ld  a1, 0(a5); \
   li a2, 0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   ld a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -533,7 +533,7 @@ test_ ## testnum: \
   fence; \
   li a1,correctval; \
   li a2,0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   ld a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -591,11 +591,11 @@ next ## testnum :
                  )
 
 #-----------------------------------------------------------------------
-# Pass and fail code (assumes test num is in x28)
+# Pass and fail code (assumes test num is in TESTNUM)
 #-----------------------------------------------------------------------
 
 #define TEST_PASSFAIL \
-        bne x0, x28, pass; \
+        bne x0, TESTNUM, pass; \
 fail: \
         RVTEST_FAIL \
 pass: \
diff --git a/isa/rv32ui/j.S b/isa/rv32ui/j.S
index 0a4ca32..ff1de65 100644
--- a/isa/rv32ui/j.S
+++ b/isa/rv32ui/j.S
@@ -15,7 +15,7 @@ RVTEST_CODE_BEGIN
   # Test basic
   #-------------------------------------------------------------
 
-  li  x28, 2;
+  li  TESTNUM, 2;
   j test_2;
   j fail;
 test_2:
diff --git a/isa/rv32ui/jal.S b/isa/rv32ui/jal.S
index c4c0af9..6055000 100644
--- a/isa/rv32ui/jal.S
+++ b/isa/rv32ui/jal.S
@@ -16,7 +16,7 @@ RVTEST_CODE_BEGIN
   #-------------------------------------------------------------
 
 test_2:
-  li  x28, 2
+  li  TESTNUM, 2
   li  ra, 0
 
 linkaddr_2:
diff --git a/isa/rv32ui/jalr.S b/isa/rv32ui/jalr.S
index 2d6d3a7..e65fd79 100644
--- a/isa/rv32ui/jalr.S
+++ b/isa/rv32ui/jalr.S
@@ -16,7 +16,7 @@ RVTEST_CODE_BEGIN
   #-------------------------------------------------------------
 
 test_2:
-  li  x28, 2
+  li  TESTNUM, 2
   li  x31, 0
   la  x2, target_2
 
@@ -37,7 +37,7 @@ target_2:
   #-------------------------------------------------------------
 
 test_3:
-  li  x28, 3
+  li  TESTNUM, 3
   li  x31, 0
   la  x3, target_3
 
diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index a636a36..fba7e78 100644
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -34,7 +34,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -63,16 +63,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL
diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index e6190c9..f03b443 100644
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -33,7 +33,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -62,16 +62,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL
diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index c16086e..6896b89 100644
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -40,7 +40,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -69,16 +69,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL
diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index ce4fe82..c240076 100644
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -48,7 +48,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -77,16 +77,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL
diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index c48e134..b139edf 100644
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -44,7 +44,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -73,16 +73,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL
diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 3879d51..56ece92 100644
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -45,7 +45,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -74,16 +74,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL
diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index d66c42f..57b6bf9 100644
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -45,7 +45,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -74,16 +74,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL
diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index 715e6a2..90eb792 100644
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -48,7 +48,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -77,16 +77,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL
diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index c8ef5ad..cd7762d 100644
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -38,7 +38,7 @@ vtcode1:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -67,16 +67,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL
diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index 1a88ca3..ef50188 100644
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -37,7 +37,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -67,16 +67,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL
diff --git a/isa/rv64ui/j.S b/isa/rv64ui/j.S
index 5b0ea3d..3c15dd3 100644
--- a/isa/rv64ui/j.S
+++ b/isa/rv64ui/j.S
@@ -15,7 +15,7 @@ RVTEST_CODE_BEGIN
   # Test basic
   #-------------------------------------------------------------
 
-  li  x28, 2;
+  li  TESTNUM, 2;
   j test_2;
   j fail;
 test_2:
diff --git a/isa/rv64ui/jal.S b/isa/rv64ui/jal.S
index f51ce1b..4881f90 100644
--- a/isa/rv64ui/jal.S
+++ b/isa/rv64ui/jal.S
@@ -16,7 +16,7 @@ RVTEST_CODE_BEGIN
   #-------------------------------------------------------------
 
 test_2:
-  li  x28, 2
+  li  TESTNUM, 2
   li  ra, 0
 
 linkaddr_2:
diff --git a/isa/rv64ui/jalr.S b/isa/rv64ui/jalr.S
index 9eef93b..cdf71e9 100644
--- a/isa/rv64ui/jalr.S
+++ b/isa/rv64ui/jalr.S
@@ -16,7 +16,7 @@ RVTEST_CODE_BEGIN
   #-------------------------------------------------------------
 
 test_2:
-  li  x28, 2
+  li  TESTNUM, 2
   li  x31, 0
   la  x2, target_2
 
@@ -37,7 +37,7 @@ target_2:
   #-------------------------------------------------------------
 
 test_3:
-  li  x28, 3
+  li  TESTNUM, 3
   li  x31, 0
   la  x3, target_3
 
diff --git a/isa/rv64uv/amoadd_d.S b/isa/rv64uv/amoadd_d.S
index 68b0ba1..64386b2 100644
--- a/isa/rv64uv/amoadd_d.S
+++ b/isa/rv64uv/amoadd_d.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
   li a1,0
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a6,a6,8
   addi a1,a1,1
diff --git a/isa/rv64uv/amoadd_w.S b/isa/rv64uv/amoadd_w.S
index ba798ef..3fcf25f 100644
--- a/isa/rv64uv/amoadd_w.S
+++ b/isa/rv64uv/amoadd_w.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
   li a1,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a6,a6,4
   addi a1,a1,1
diff --git a/isa/rv64uv/amoand_d.S b/isa/rv64uv/amoand_d.S
index b2dc699..f997ab0 100644
--- a/isa/rv64uv/amoand_d.S
+++ b/isa/rv64uv/amoand_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1
diff --git a/isa/rv64uv/amoand_w.S b/isa/rv64uv/amoand_w.S
index 726033d..7cc39ea 100644
--- a/isa/rv64uv/amoand_w.S
+++ b/isa/rv64uv/amoand_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1
diff --git a/isa/rv64uv/amomax_d.S b/isa/rv64uv/amomax_d.S
index aafdf75..c376b0e 100644
--- a/isa/rv64uv/amomax_d.S
+++ b/isa/rv64uv/amomax_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1
diff --git a/isa/rv64uv/amomax_w.S b/isa/rv64uv/amomax_w.S
index 0308991..ec1c098 100644
--- a/isa/rv64uv/amomax_w.S
+++ b/isa/rv64uv/amomax_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1
diff --git a/isa/rv64uv/amomaxu_d.S b/isa/rv64uv/amomaxu_d.S
index 95d8fce..696fb85 100644
--- a/isa/rv64uv/amomaxu_d.S
+++ b/isa/rv64uv/amomaxu_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1
diff --git a/isa/rv64uv/amomaxu_w.S b/isa/rv64uv/amomaxu_w.S
index feac563..3d7fd63 100644
--- a/isa/rv64uv/amomaxu_w.S
+++ b/isa/rv64uv/amomaxu_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1
diff --git a/isa/rv64uv/amomin_d.S b/isa/rv64uv/amomin_d.S
index 6fd9d27..5215c3b 100644
--- a/isa/rv64uv/amomin_d.S
+++ b/isa/rv64uv/amomin_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   ld a0,0(a5)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a5,a5,8
   addi a1,a1,1
diff --git a/isa/rv64uv/amomin_w.S b/isa/rv64uv/amomin_w.S
index 44260f2..0b822fa 100644
--- a/isa/rv64uv/amomin_w.S
+++ b/isa/rv64uv/amomin_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1
diff --git a/isa/rv64uv/amominu_d.S b/isa/rv64uv/amominu_d.S
index 3f5f7ab..4c0b31f 100644
--- a/isa/rv64uv/amominu_d.S
+++ b/isa/rv64uv/amominu_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1
diff --git a/isa/rv64uv/amominu_w.S b/isa/rv64uv/amominu_w.S
index 56f3a7d..1cc8b24 100644
--- a/isa/rv64uv/amominu_w.S
+++ b/isa/rv64uv/amominu_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1
diff --git a/isa/rv64uv/amoor_d.S b/isa/rv64uv/amoor_d.S
index 76d553c..833f056 100644
--- a/isa/rv64uv/amoor_d.S
+++ b/isa/rv64uv/amoor_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1
diff --git a/isa/rv64uv/amoor_w.S b/isa/rv64uv/amoor_w.S
index 9d0bd2f..c948c32 100644
--- a/isa/rv64uv/amoor_w.S
+++ b/isa/rv64uv/amoor_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1
diff --git a/isa/rv64uv/amoswap_d.S b/isa/rv64uv/amoswap_d.S
index df98556..0e3db8f 100644
--- a/isa/rv64uv/amoswap_d.S
+++ b/isa/rv64uv/amoswap_d.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a1,0
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a6,a6,8
   addi a1,a1,1
diff --git a/isa/rv64uv/amoswap_w.S b/isa/rv64uv/amoswap_w.S
index c068569..6a5b1fb 100644
--- a/isa/rv64uv/amoswap_w.S
+++ b/isa/rv64uv/amoswap_w.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a1,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a6,a6,4
   addi a1,a1,1
diff --git a/isa/rv64uv/amoxor_d.S b/isa/rv64uv/amoxor_d.S
index f67bccf..7f84fd5 100644
--- a/isa/rv64uv/amoxor_d.S
+++ b/isa/rv64uv/amoxor_d.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
   li t0,0xaaaaaaaaaaaaaaaa
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1
diff --git a/isa/rv64uv/amoxor_w.S b/isa/rv64uv/amoxor_w.S
index fac070f..602634d 100644
--- a/isa/rv64uv/amoxor_w.S
+++ b/isa/rv64uv/amoxor_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1
diff --git a/isa/rv64uv/fcvt.S b/isa/rv64uv/fcvt.S
index 227a154..cb8e98c 100644
--- a/isa/rv64uv/fcvt.S
+++ b/isa/rv64uv/fcvt.S
@@ -25,19 +25,19 @@ RVTEST_CODE_BEGIN
   la a5,result
   ld a1,0(a4)
   ld a2,0(a5)
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a4)
   ld a2,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a4)
   ld a2,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a4)
   ld a2,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass
 
diff --git a/isa/rv64uv/fld.S b/isa/rv64uv/fld.S
index d41e761..37e05e0 100644
--- a/isa/rv64uv/fld.S
+++ b/isa/rv64uv/fld.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   ld a0,0(a6)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   ld a1,0(a5)
   bne a0,a1,fail
   addi a6,a6,8
diff --git a/isa/rv64uv/flw.S b/isa/rv64uv/flw.S
index 7e940f6..0284489 100644
--- a/isa/rv64uv/flw.S
+++ b/isa/rv64uv/flw.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   lw a1,0(a5)
   bne a0,a1,fail
   addi a6,a6,4
diff --git a/isa/rv64uv/fma.S b/isa/rv64uv/fma.S
index e875c61..c4489ae 100644
--- a/isa/rv64uv/fma.S
+++ b/isa/rv64uv/fma.S
@@ -40,13 +40,13 @@ wait:
 
   la s3,result
   ld s4,0(s3)
-  li x28,2
+  li TESTNUM,2
   bne s2,s4,fail
 
   li a2,0
 loop:
   ld a0,0(a5)
-  addi x28,a2,3
+  addi TESTNUM,a2,3
   bne a0,s4,fail
   addi a5,a5,8
   addi a2,a2,1
diff --git a/isa/rv64uv/fmovn.S b/isa/rv64uv/fmovn.S
index 47a6a39..6c54b5e 100644
--- a/isa/rv64uv/fmovn.S
+++ b/isa/rv64uv/fmovn.S
@@ -29,7 +29,7 @@ loop:
   slli a4,a4,63
   srai a4,a4,63
   and a5,a2,a4
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a5,fail
   addi a7,a7,8
   addi a1,a1,1
diff --git a/isa/rv64uv/fmovz.S b/isa/rv64uv/fmovz.S
index f3e09b6..4f55cdc 100644
--- a/isa/rv64uv/fmovz.S
+++ b/isa/rv64uv/fmovz.S
@@ -30,7 +30,7 @@ loop:
   srai a4,a4,63
   xori a4,a4,-1
   and a5,a2,a4
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a5,fail
   addi a7,a7,8
   addi a1,a1,1
diff --git a/isa/rv64uv/fsd.S b/isa/rv64uv/fsd.S
index f220679..c871e09 100644
--- a/isa/rv64uv/fsd.S
+++ b/isa/rv64uv/fsd.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   ld a0,0(a6)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   ld a1,0(a5)
   bne a0,a1,fail
   addi a6,a6,8
diff --git a/isa/rv64uv/fsw.S b/isa/rv64uv/fsw.S
index 71c1d2f..7c78df5 100644
--- a/isa/rv64uv/fsw.S
+++ b/isa/rv64uv/fsw.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   lw a1,0(a5)
   bne a0,a1,fail
   addi a6,a6,4
diff --git a/isa/rv64uv/imul.S b/isa/rv64uv/imul.S
index 1b3a2dd..554374d 100644
--- a/isa/rv64uv/imul.S
+++ b/isa/rv64uv/imul.S
@@ -48,14 +48,14 @@ RVTEST_CODE_BEGIN
   fence
 
   li s2,40
-  li x28,2
+  li TESTNUM,2
   bne s1,s2,fail
 
   li a1,0
   li a2,0
 loop:
   ld a0,0(a5)
-  addi x28,a2,3
+  addi TESTNUM,a2,3
   bne a0,a1,fail
   addi a5,a5,8
   addi a1,a1,20
diff --git a/isa/rv64uv/lb.S b/isa/rv64uv/lb.S
index 46ca639..471199a 100644
--- a/isa/rv64uv/lb.S
+++ b/isa/rv64uv/lb.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,56
   sra a3,a3,56
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/lbu.S b/isa/rv64uv/lbu.S
index 47c2261..2aa5ee8 100644
--- a/isa/rv64uv/lbu.S
+++ b/isa/rv64uv/lbu.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,56
   srl a3,a3,56
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/ld.S b/isa/rv64uv/ld.S
index 354ee38..0794192 100644
--- a/isa/rv64uv/ld.S
+++ b/isa/rv64uv/ld.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
 loop:
   ld a0,0(a6)
   ld a1,0(a5)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a1,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/lh.S b/isa/rv64uv/lh.S
index e4ff176..a24146c 100644
--- a/isa/rv64uv/lh.S
+++ b/isa/rv64uv/lh.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,48
   sra a3,a3,48
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/lhu.S b/isa/rv64uv/lhu.S
index dadf99b..e20d56d 100644
--- a/isa/rv64uv/lhu.S
+++ b/isa/rv64uv/lhu.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,48
   srl a3,a3,48
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/lw.S b/isa/rv64uv/lw.S
index 182dc89..b40ec47 100644
--- a/isa/rv64uv/lw.S
+++ b/isa/rv64uv/lw.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,32
   sra a3,a3,32
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/lwu.S b/isa/rv64uv/lwu.S
index d6df839..0b3591a 100644
--- a/isa/rv64uv/lwu.S
+++ b/isa/rv64uv/lwu.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,32
   srl a3,a3,32
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/movz.S b/isa/rv64uv/movz.S
index 374b271..790edce 100644
--- a/isa/rv64uv/movz.S
+++ b/isa/rv64uv/movz.S
@@ -30,7 +30,7 @@ loop:
   srai a4,a4,63
   xori a4,a4,-1
   and a5,a2,a4
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a5,fail
   addi a7,a7,8
   addi a1,a1,1
diff --git a/isa/rv64uv/sb.S b/isa/rv64uv/sb.S
index 5cbe76a..b9954ed 100644
--- a/isa/rv64uv/sb.S
+++ b/isa/rv64uv/sb.S
@@ -39,7 +39,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,56
   srl a3,a3,56
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/sd.S b/isa/rv64uv/sd.S
index 053c401..5ec8051 100644
--- a/isa/rv64uv/sd.S
+++ b/isa/rv64uv/sd.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
 loop:
   ld a0,0(a6)
   ld a1,0(a5)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a1,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/sh.S b/isa/rv64uv/sh.S
index 25bb258..0177010 100644
--- a/isa/rv64uv/sh.S
+++ b/isa/rv64uv/sh.S
@@ -39,7 +39,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,48
   srl a3,a3,48
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/sw.S b/isa/rv64uv/sw.S
index 8f1599b..6196720 100644
--- a/isa/rv64uv/sw.S
+++ b/isa/rv64uv/sw.S
@@ -39,7 +39,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,32
   srl a3,a3,32
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8
diff --git a/isa/rv64uv/utidx.S b/isa/rv64uv/utidx.S
index 0439115..a672776 100644
--- a/isa/rv64uv/utidx.S
+++ b/isa/rv64uv/utidx.S
@@ -24,7 +24,7 @@ RVTEST_CODE_BEGIN
   li a1,1
 loop:
   ld a0,0(a4)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a4,a4,8
   addi a1,a1,1
diff --git a/isa/rv64uv/vfmvv.S b/isa/rv64uv/vfmvv.S
index 68e085e..cb97dee 100644
--- a/isa/rv64uv/vfmvv.S
+++ b/isa/rv64uv/vfmvv.S
@@ -25,7 +25,7 @@ RVTEST_CODE_BEGIN
   li a1,1
 loop:
   ld a0,0(a3)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a3,a3,8
   addi a1,a1,1
diff --git a/isa/rv64uv/vmsv.S b/isa/rv64uv/vmsv.S
index d469e59..773188d 100644
--- a/isa/rv64uv/vmsv.S
+++ b/isa/rv64uv/vmsv.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a1,0
 loop:
   ld a0,0(a4)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a4,a4,8
   addi a1,a1,1
diff --git a/isa/rv64uv/vmvv.S b/isa/rv64uv/vmvv.S
index be1adb3..b546f05 100644
--- a/isa/rv64uv/vmvv.S
+++ b/isa/rv64uv/vmvv.S
@@ -25,7 +25,7 @@ RVTEST_CODE_BEGIN
   li a1,1
 loop:
   ld a0,0(a4)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a4,a4,8
   addi a1,a1,1
diff --git a/isa/rv64uv/vvadd_branch.S b/isa/rv64uv/vvadd_branch.S
index 5f9f3a4..4c3fefe 100644
--- a/isa/rv64uv/vvadd_branch.S
+++ b/isa/rv64uv/vvadd_branch.S
@@ -27,19 +27,19 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,8
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
   li a2, 6        
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
   li a2, 4        
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   li a2, 2
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   la a3,src1
@@ -54,19 +54,19 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,1
-  li x28,6
+  li TESTNUM,6
   bne a1,a2,fail
   ld a1,8(a5)
   li a2,2
-  li x28,7
+  li TESTNUM,7
   bne a1,a2,fail
   ld a1,16(a5)
   li a2,0
-  li x28,8
+  li TESTNUM,8
   bne a1,a2,fail
   ld a1,24(a5)
   li a2,0
-  li x28,9
+  li TESTNUM,9
   bne a1,a2,fail
 
   la a3,src2
@@ -79,19 +79,19 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,4
-  li x28,6
+  li TESTNUM,6
   bne a1,a2,fail
   ld a1,8(a5)
   li a2,3
-  li x28,7
+  li TESTNUM,7
   bne a1,a2,fail
   ld a1,16(a5)
   li a2,2
-  li x28,8
+  li TESTNUM,8
   bne a1,a2,fail
   ld a1,24(a5)
   li a2,1
-  li x28,9
+  li TESTNUM,9
   bne a1,a2,fail
 
   j pass
diff --git a/isa/rv64uv/vvadd_d.S b/isa/rv64uv/vvadd_d.S
index 8875b95..e1acea7 100644
--- a/isa/rv64uv/vvadd_d.S
+++ b/isa/rv64uv/vvadd_d.S
@@ -27,16 +27,16 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   la a3,src1
@@ -49,19 +49,19 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,1
-  li x28,6
+  li TESTNUM,6
   bne a1,a2,fail
   ld a1,8(a5)
   li a2,2
-  li x28,7
+  li TESTNUM,7
   bne a1,a2,fail
   ld a1,16(a5)
   li a2,3
-  li x28,8
+  li TESTNUM,8
   bne a1,a2,fail
   ld a1,24(a5)
   li a2,4
-  li x28,9
+  li TESTNUM,9
   bne a1,a2,fail
 
   la a3,src2
@@ -74,19 +74,19 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,4
-  li x28,6
+  li TESTNUM,6
   bne a1,a2,fail
   ld a1,8(a5)
   li a2,3
-  li x28,7
+  li TESTNUM,7
   bne a1,a2,fail
   ld a1,16(a5)
   li a2,2
-  li x28,8
+  li TESTNUM,8
   bne a1,a2,fail
   ld a1,24(a5)
   li a2,1
-  li x28,9
+  li TESTNUM,9
   bne a1,a2,fail
 
   j pass
diff --git a/isa/rv64uv/vvadd_fd.S b/isa/rv64uv/vvadd_fd.S
index 62161ef..a9961af 100644
--- a/isa/rv64uv/vvadd_fd.S
+++ b/isa/rv64uv/vvadd_fd.S
@@ -27,16 +27,16 @@ RVTEST_CODE_BEGIN
   la a6,result
   ld a1,0(a5)
   ld a2,0(a6)
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass
 
diff --git a/isa/rv64uv/vvadd_fw.S b/isa/rv64uv/vvadd_fw.S
index 916002f..e40fd01 100644
--- a/isa/rv64uv/vvadd_fw.S
+++ b/isa/rv64uv/vvadd_fw.S
@@ -27,16 +27,16 @@ RVTEST_CODE_BEGIN
   la a6,result
   lw a1,0(a5)
   lw a2,0(a6)
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   lw a1,4(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   lw a1,8(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   lw a1,12(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass
 
diff --git a/isa/rv64uv/vvadd_w.S b/isa/rv64uv/vvadd_w.S
index f81c42e..9fbcf49 100644
--- a/isa/rv64uv/vvadd_w.S
+++ b/isa/rv64uv/vvadd_w.S
@@ -26,16 +26,16 @@ RVTEST_CODE_BEGIN
   fence
   lw a1,0(a5)
   li a2,10
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   lw a1,4(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   lw a1,8(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   lw a1,12(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass
 
diff --git a/isa/rv64uv/vvmul_d.S b/isa/rv64uv/vvmul_d.S
index a6a9d4a..ae995c9 100644
--- a/isa/rv64uv/vvmul_d.S
+++ b/isa/rv64uv/vvmul_d.S
@@ -26,19 +26,19 @@ RVTEST_CODE_BEGIN
   fence
   ld a1,0(a5)
   li a2,4
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
   li a2,6
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
   li a2,6
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
   li a2,4
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass
 
diff --git a/isa/rv64uv/wakeup.S b/isa/rv64uv/wakeup.S
index 008423a..958f668 100644
--- a/isa/rv64uv/wakeup.S
+++ b/isa/rv64uv/wakeup.S
@@ -29,35 +29,35 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,0xdeadbeefcafebabe
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   # check default hw vector length, which is 32
   li a3, 32
   vsetvl a3, a3
   li a0, 32
-  li x28, 6
+  li TESTNUM, 6
   bne a3, a0, fail
 
   li a3, 33
   vsetvl a3, a3
   li a0, 32
-  li x28, 7
+  li TESTNUM, 7
   bne a3, a0, fail
 
   li a3, 31
   vsetvl a3, a3
   li a0, 31
-  li x28, 8
+  li TESTNUM, 8
   bne a3, a0, fail
 
   # now do some vector stuff without vsetcfg
@@ -77,16 +77,16 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,5
-  li x28,9
+  li TESTNUM,9
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,10
+  li TESTNUM,10
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,11
+  li TESTNUM,11
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,12
+  li TESTNUM,12
   bne a1,a2,fail
 
   # initialize dest memory
@@ -112,16 +112,16 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,0xdeadbeefcafebabe
-  li x28,13
+  li TESTNUM,13
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,14
+  li TESTNUM,14
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,15
+  li TESTNUM,15
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,16
+  li TESTNUM,16
   bne a1,a2,fail
 
   j pass