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authorCarsten Gosvig <40368726+cgsfv@users.noreply.github.com>2019-01-25 11:27:12 +0100
committerGitHub <noreply@github.com>2019-01-25 11:27:12 +0100
commit4469fecaaefe273848c46885153dfadeb2ed70ed (patch)
tree43fbb30f8cc370c54622869d1ad3aaf018a89388
parenta77db03bf0344cfc102d9957e1d58f0d2ece58d5 (diff)
parenta5d280990e7d258b76d2154c83ecae271511426c (diff)
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Merge pull request #175 from riscv/test_rti
Add testing of run-test/idle cases.
-rw-r--r--debug/targets/RISC-V/spike32-2-rtos.py2
-rw-r--r--debug/targets/RISC-V/spike32-2.py2
-rw-r--r--debug/targets/RISC-V/spike32.py2
-rw-r--r--debug/targets/RISC-V/spike64-2-rtos.py2
-rw-r--r--debug/targets/RISC-V/spike64-2.py2
-rw-r--r--debug/targets/RISC-V/spike64.py3
-rw-r--r--debug/testlib.py11
7 files changed, 17 insertions, 7 deletions
diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py
index c45013f..a2951c1 100644
--- a/debug/targets/RISC-V/spike32-2-rtos.py
+++ b/debug/targets/RISC-V/spike32-2-rtos.py
@@ -10,4 +10,4 @@ class spike32_2(targets.Target):
implements_custom_test = True
def create(self):
- return testlib.Spike(self, progbufsize=0)
+ return testlib.Spike(self, progbufsize=0, dmi_rti=4)
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index 6c90b7c..8872ad3 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -10,4 +10,4 @@ class spike32_2(targets.Target):
implements_custom_test = True
def create(self):
- return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0)
+ return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4)
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index a831ecb..e633eea 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -17,4 +17,4 @@ class spike32(targets.Target):
def create(self):
# 64-bit FPRs on 32-bit target
- return testlib.Spike(self, isa="RV32IMAFDC")
+ return testlib.Spike(self, isa="RV32IMAFDC", dmi_rti=4)
diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py
index 9cb3a44..1da7116 100644
--- a/debug/targets/RISC-V/spike64-2-rtos.py
+++ b/debug/targets/RISC-V/spike64-2-rtos.py
@@ -10,4 +10,4 @@ class spike64_2_rtos(targets.Target):
implements_custom_test = True
def create(self):
- return testlib.Spike(self)
+ return testlib.Spike(self, abstract_rti=30)
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index 23ae06b..e981105 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -10,4 +10,4 @@ class spike64_2(targets.Target):
implements_custom_test = True
def create(self):
- return testlib.Spike(self, isa="RV64IMAFD")
+ return testlib.Spike(self, isa="RV64IMAFD", abstract_rti=30)
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index d0eaf5c..fdb1282 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -17,4 +17,5 @@ class spike64(targets.Target):
def create(self):
# 32-bit FPRs only
- return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0)
+ return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0,
+ abstract_rti=30)
diff --git a/debug/testlib.py b/debug/testlib.py
index 8fa0c43..a302cc6 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -56,13 +56,16 @@ def compile(args, xlen=32): # pylint: disable=redefined-builtin
raise Exception("Compile failed!")
class Spike(object):
+ # pylint: disable=too-many-instance-attributes
def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
- isa=None, progbufsize=None):
+ isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None):
"""Launch spike. Return tuple of its process and the port it's running
on."""
self.process = None
self.isa = isa
self.progbufsize = progbufsize
+ self.dmi_rti = dmi_rti
+ self.abstract_rti = abstract_rti
if target.harts:
harts = target.harts
@@ -124,6 +127,12 @@ class Spike(object):
cmd += ["--progsize", str(self.progbufsize)]
cmd += ["--debug-sba", "32"]
+ if not self.dmi_rti is None:
+ cmd += ["--dmi-rti", str(self.dmi_rti)]
+
+ if not self.abstract_rti is None:
+ cmd += ["--abstract-rti", str(self.abstract_rti)]
+
assert len(set(t.ram for t in harts)) == 1, \
"All spike harts must have the same RAM layout"
assert len(set(t.ram_size for t in harts)) == 1, \