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| author | Tim Newsome <tim@sifive.com> | 2017-08-11 12:55:25 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-08-28 12:16:39 -0700 |
| commit | 28fbcac967d6c2a0085faa2007c98d64d3203491 (patch) | |
| tree | b1c4e051296db207ddbd13d56d25aa01a7627e81 | |
| parent | efe2f16d12c23eca1e66d2a304d89aafb22f005f (diff) | |
| download | riscv-tests-28fbcac967d6c2a0085faa2007c98d64d3203491.zip riscv-tests-28fbcac967d6c2a0085faa2007c98d64d3203491.tar.gz riscv-tests-28fbcac967d6c2a0085faa2007c98d64d3203491.tar.bz2 | |
Make pylint happy.
| -rw-r--r-- | debug/targets/RISC-V/spike32-2.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2.py | 2 | ||||
| -rw-r--r-- | debug/targets/SiFive/Freedom/U500Sim.py | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index 3f87d26..09bab1d 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -1,7 +1,7 @@ import targets import testlib -import spike32 +import spike32 # pylint: disable=import-error class spike32_2(targets.Target): harts = [spike32.spike32_hart(), spike32.spike32_hart()] diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index e1df6d2..f2e0a8a 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -1,7 +1,7 @@ import targets import testlib -import spike64 +import spike64 # pylint: disable=import-error class spike64_2(targets.Target): harts = [spike64.spike64_hart(), spike64.spike64_hart()] diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py index 5c500c4..065ab08 100644 --- a/debug/targets/SiFive/Freedom/U500Sim.py +++ b/debug/targets/SiFive/Freedom/U500Sim.py @@ -8,7 +8,7 @@ class U500Hart(targets.Hart): instruction_hardware_breakpoint_count = 2 link_script_path = "Freedom.lds" -class U500Sim(Target): +class U500Sim(targets.Target): timeout_sec = 6000 openocd_config_path = "Freedom.cfg" harts = [U500Hart()] |