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| author | Andrew Waterman <andrew@sifive.com> | 2017-09-20 10:47:11 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-10-26 21:36:13 -0700 |
| commit | 7b4922e130bb520f9328dca77cf7330df96ce2f9 (patch) | |
| tree | e8db8b4415cc16fa941053b11590c123778f6199 | |
| parent | bb14a75c0b938dcbb308a5304ea0c3f30c3fceef (diff) | |
| download | riscv-tests-7b4922e130bb520f9328dca77cf7330df96ce2f9.zip riscv-tests-7b4922e130bb520f9328dca77cf7330df96ce2f9.tar.gz riscv-tests-7b4922e130bb520f9328dca77cf7330df96ce2f9.tar.bz2 | |
Verify that mtval/stval is written correctly on misaligned fetch
| -rw-r--r-- | isa/rv64si/ma_fetch.S | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S index d4e5b44..eb50f94 100644 --- a/isa/rv64si/ma_fetch.S +++ b/isa/rv64si/ma_fetch.S @@ -17,6 +17,7 @@ RVTEST_CODE_BEGIN #define sscratch mscratch #define sstatus mstatus #define scause mcause + #define sbadaddr mbadaddr #define sepc mepc #define sret mret #define stvec_handler mtvec_handler @@ -132,9 +133,16 @@ stvec_handler: # verify that epc == &jalr (== t0 - 4) csrr a1, sepc - addi t0, t0, -4 + addi a1, a1, 4 bne t0, a1, fail + # verify that badaddr == 0 or badaddr == t0+2. + csrr a0, sbadaddr + beqz a0, 1f + addi a0, a0, -2 + bne a0, t0, fail +1: + addi a1, a1, 12 csrw sepc, a1 sret |