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| author | Tim Newsome <tim@sifive.com> | 2018-08-22 13:47:26 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-08-22 13:47:26 -0700 |
| commit | 995207c1196d970173e1513535e8341542111102 (patch) | |
| tree | 91064f788f2f307d6f671335f60cb5b938345713 | |
| parent | 51ec34e28541f8c89cd89a6a9c137bd32ba71c29 (diff) | |
| parent | 5b4eb413c2620d4f29af1a8954871a74be8dee25 (diff) | |
| download | riscv-tests-995207c1196d970173e1513535e8341542111102.zip riscv-tests-995207c1196d970173e1513535e8341542111102.tar.gz riscv-tests-995207c1196d970173e1513535e8341542111102.tar.bz2 | |
Merge branch 'master' of https://github.com/riscv/riscv-tests
| -rw-r--r-- | isa/rv64si/scall.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S index 0579806..82f202a 100644 --- a/isa/rv64si/scall.S +++ b/isa/rv64si/scall.S @@ -34,8 +34,8 @@ RVTEST_CODE_BEGIN # Otherwise, if in S mode, then U mode must exist and we don't need to check. li t0, MSTATUS_MPP csrc mstatus, t0 - csrr t1, mstatus - and t0, t0, t1 + csrr t2, mstatus + and t0, t0, t2 beqz t0, 1f # If U mode doesn't exist, mcause should indicate ECALL from M mode. |