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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-05-02 04:41:37 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-05-02 04:41:37 -0700 |
| commit | 1dd1e13180dd65ffe3075cbdc5c12fda8c3e755f (patch) | |
| tree | 823a31838ece3f9a273bbca2151c335dae63da9f | |
| parent | be72d6bacf1a14b85b142092bc47e4bfe68b38fd (diff) | |
| download | riscv-tests-1dd1e13180dd65ffe3075cbdc5c12fda8c3e755f.zip riscv-tests-1dd1e13180dd65ffe3075cbdc5c12fda8c3e755f.tar.gz riscv-tests-1dd1e13180dd65ffe3075cbdc5c12fda8c3e755f.tar.bz2 | |
use RVTEST_RV64UF macro for FPU tests
| -rw-r--r-- | env/p/riscv_test.h | 4 | ||||
| -rw-r--r-- | env/pm/riscv_test.h | 4 | ||||
| -rw-r--r-- | env/pt/riscv_test.h | 4 | ||||
| -rw-r--r-- | env/v/riscv_test.h | 14 | ||||
| -rw-r--r-- | isa/rv64uf/fadd.S | 2 | ||||
| -rw-r--r-- | isa/rv64uf/fcmp.S | 2 | ||||
| -rw-r--r-- | isa/rv64uf/fcvt.S | 2 | ||||
| -rw-r--r-- | isa/rv64uf/fcvt_w.S | 2 | ||||
| -rw-r--r-- | isa/rv64uf/fmadd.S | 2 | ||||
| -rw-r--r-- | isa/rv64uf/fmin.S | 2 | ||||
| -rw-r--r-- | isa/rv64uf/fsgnj.S | 2 | ||||
| -rw-r--r-- | isa/rv64uf/ldst.S | 2 | ||||
| -rw-r--r-- | isa/rv64uf/move.S | 2 | ||||
| -rw-r--r-- | isa/rv64uf/structural.S | 2 |
14 files changed, 32 insertions, 14 deletions
diff --git a/env/p/riscv_test.h b/env/p/riscv_test.h index 8ce8490..a537fb2 100644 --- a/env/p/riscv_test.h +++ b/env/p/riscv_test.h @@ -7,6 +7,10 @@ #define RVTEST_RV64U \ +#define RVTEST_RV64UF \ + RVTEST_RV64U; \ + RVTEST_FP_ENABLE + #define RVTEST_RV32U \ clearpcr cr0, 0x80 diff --git a/env/pm/riscv_test.h b/env/pm/riscv_test.h index fd07ead..98d0580 100644 --- a/env/pm/riscv_test.h +++ b/env/pm/riscv_test.h @@ -7,6 +7,10 @@ #define RVTEST_RV64U \ +#define RVTEST_RV64UF \ + RVTEST_RV64U; \ + RVTEST_FP_ENABLE + #define RVTEST_RV64S \ #define RVTEST_FP_ENABLE \ diff --git a/env/pt/riscv_test.h b/env/pt/riscv_test.h index 363e6e1..748fe97 100644 --- a/env/pt/riscv_test.h +++ b/env/pt/riscv_test.h @@ -9,6 +9,10 @@ #define RVTEST_RV64U \ +#define RVTEST_RV64UF \ + RVTEST_RV64U; \ + RVTEST_FP_ENABLE + #define RVTEST_FP_ENABLE \ setpcr cr0, 2; \ mfpcr a0, cr0; \ diff --git a/env/v/riscv_test.h b/env/v/riscv_test.h index 2a1710d..6aa232e 100644 --- a/env/v/riscv_test.h +++ b/env/v/riscv_test.h @@ -6,11 +6,17 @@ //----------------------------------------------------------------------- #define RVTEST_RV64U \ + .text; \ +init: \ + ret -#define RVTEST_RV64S \ - -#define RVTEST_FP_ENABLE \ +#define RVTEST_RV64UF \ + .text; \ +init: \ mtfsr x0; \ + ret + +#define RVTEST_RV64S \ #define RVTEST_VEC_ENABLE \ mfpcr t0, cr0; \ @@ -24,7 +30,7 @@ .align 13; \ .global userstart; \ userstart: \ - RVTEST_FP_ENABLE; \ + jal init //----------------------------------------------------------------------- // End Macro diff --git a/isa/rv64uf/fadd.S b/isa/rv64uf/fadd.S index 58f44be..cced11b 100644 --- a/isa/rv64uf/fadd.S +++ b/isa/rv64uf/fadd.S @@ -8,7 +8,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UF RVTEST_CODE_BEGIN #------------------------------------------------------------- diff --git a/isa/rv64uf/fcmp.S b/isa/rv64uf/fcmp.S index 845db3c..21cbf9d 100644 --- a/isa/rv64uf/fcmp.S +++ b/isa/rv64uf/fcmp.S @@ -8,7 +8,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UF RVTEST_CODE_BEGIN #------------------------------------------------------------- diff --git a/isa/rv64uf/fcvt.S b/isa/rv64uf/fcvt.S index bb9a9c4..0e83416 100644 --- a/isa/rv64uf/fcvt.S +++ b/isa/rv64uf/fcvt.S @@ -8,7 +8,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UF RVTEST_CODE_BEGIN #------------------------------------------------------------- diff --git a/isa/rv64uf/fcvt_w.S b/isa/rv64uf/fcvt_w.S index e2e1686..5492a09 100644 --- a/isa/rv64uf/fcvt_w.S +++ b/isa/rv64uf/fcvt_w.S @@ -8,7 +8,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UF RVTEST_CODE_BEGIN #------------------------------------------------------------- diff --git a/isa/rv64uf/fmadd.S b/isa/rv64uf/fmadd.S index 76e5e9f..dc16ecb 100644 --- a/isa/rv64uf/fmadd.S +++ b/isa/rv64uf/fmadd.S @@ -8,7 +8,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UF RVTEST_CODE_BEGIN #------------------------------------------------------------- diff --git a/isa/rv64uf/fmin.S b/isa/rv64uf/fmin.S index 0041ea5..f9e8dda 100644 --- a/isa/rv64uf/fmin.S +++ b/isa/rv64uf/fmin.S @@ -8,7 +8,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UF RVTEST_CODE_BEGIN #------------------------------------------------------------- diff --git a/isa/rv64uf/fsgnj.S b/isa/rv64uf/fsgnj.S index 0d2124b..d405564 100644 --- a/isa/rv64uf/fsgnj.S +++ b/isa/rv64uf/fsgnj.S @@ -8,7 +8,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UF RVTEST_CODE_BEGIN #------------------------------------------------------------- diff --git a/isa/rv64uf/ldst.S b/isa/rv64uf/ldst.S index f37a478..653344b 100644 --- a/isa/rv64uf/ldst.S +++ b/isa/rv64uf/ldst.S @@ -8,7 +8,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UF RVTEST_CODE_BEGIN TEST_CASE(2, a0, 0x4000000040400000, la a1, tdat; flw f1, 4(a1); fsw f1, 12(a1); ld a0, 8(a1)) diff --git a/isa/rv64uf/move.S b/isa/rv64uf/move.S index f06e324..d8ad24c 100644 --- a/isa/rv64uf/move.S +++ b/isa/rv64uf/move.S @@ -9,7 +9,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UF RVTEST_CODE_BEGIN li a0, 1 diff --git a/isa/rv64uf/structural.S b/isa/rv64uf/structural.S index 0c74ab5..24a5687 100644 --- a/isa/rv64uf/structural.S +++ b/isa/rv64uf/structural.S @@ -9,7 +9,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64U +RVTEST_RV64UF RVTEST_CODE_BEGIN li x25, 1 |