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| author | Tim Newsome <tim@sifive.com> | 2020-03-18 12:24:49 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-18 12:24:49 -0700 |
| commit | b436c737c52ff1a5e2957ffc588114f9415e3b3a (patch) | |
| tree | 2ae6bb6091c329d0bf4300c5a07bbcac180c5647 | |
| parent | 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5 (diff) | |
| download | riscv-tests-b436c737c52ff1a5e2957ffc588114f9415e3b3a.zip riscv-tests-b436c737c52ff1a5e2957ffc588114f9415e3b3a.tar.gz riscv-tests-b436c737c52ff1a5e2957ffc588114f9415e3b3a.tar.bz2 | |
Specify misa for HiFive Unleashed. (#259)
This saves a few seconds every time I run any test.
| -rw-r--r-- | debug/targets/SiFive/HiFiveUnleashed.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/debug/targets/SiFive/HiFiveUnleashed.py b/debug/targets/SiFive/HiFiveUnleashed.py index dd92a53..9bf7cae 100644 --- a/debug/targets/SiFive/HiFiveUnleashed.py +++ b/debug/targets/SiFive/HiFiveUnleashed.py @@ -6,6 +6,7 @@ class E51(targets.Hart): ram_size = 1024 * 1024 instruction_hardware_breakpoint_count = 2 reset_vectors = [0x1004] + misa = 0x8000000000101105 class U54(targets.Hart): xlen = 64 @@ -13,6 +14,7 @@ class U54(targets.Hart): ram_size = 1024 * 1024 instruction_hardware_breakpoint_count = 2 reset_vectors = [0x1004] + misa = 0x800000000014112d class HiFiveUnleashed(targets.Target): support_hasel = False |