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| author | Tim Newsome <tim@sifive.com> | 2020-03-18 12:25:02 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-18 12:25:02 -0700 |
| commit | 6c53e59231b3834d98c124e54e3dcef822038b7f (patch) | |
| tree | 740783e156463babbefd7bdb16e6db0f7ccf58cc | |
| parent | b436c737c52ff1a5e2957ffc588114f9415e3b3a (diff) | |
| download | riscv-tests-6c53e59231b3834d98c124e54e3dcef822038b7f.zip riscv-tests-6c53e59231b3834d98c124e54e3dcef822038b7f.tar.gz riscv-tests-6c53e59231b3834d98c124e54e3dcef822038b7f.tar.bz2 | |
Spike changed --varch syntax (#257)
This was changed by https://github.com/riscv/riscv-isa-sim/pull/417
| -rw-r--r-- | debug/testlib.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/debug/testlib.py b/debug/testlib.py index f820aaf..d969999 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -145,8 +145,8 @@ class Spike: cmd.append("--dm-no-halt-groups") if 'V' in isa[2:]: - cmd.append("--varch=v%d:e%d:s%d" % (self.vlen, self.elen, - self.slen)) + cmd.append("--varch=vlen:%d,elen:%d,slen:%d" % (self.vlen, + self.elen, self.slen)) assert len(set(t.ram for t in harts)) == 1, \ "All spike harts must have the same RAM layout" |