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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-25 16:07:25 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-25 16:07:25 -0700 |
| commit | f9e8b267a273eb704f6def6f0fa04140d0654d18 (patch) | |
| tree | 834161450dbddb5796857a2bd37e29dbcf8ee9fe | |
| parent | 8aebc7e29009096e0c5bd2a3ab7bc31271647020 (diff) | |
| download | riscv-tests-f9e8b267a273eb704f6def6f0fa04140d0654d18.zip riscv-tests-f9e8b267a273eb704f6def6f0fa04140d0654d18.tar.gz riscv-tests-f9e8b267a273eb704f6def6f0fa04140d0654d18.tar.bz2 | |
Fix FPU initialization code
| -rw-r--r-- | benchmarks/common/crt.S | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S index be03ebb..3d4d6cf 100644 --- a/benchmarks/common/crt.S +++ b/benchmarks/common/crt.S @@ -15,9 +15,6 @@ .section ".text.init" .globl _start _start: - la t0, trap_entry - csrw mtvec, t0 - li x1, 0 li x2, 0 li x3, 0 @@ -62,14 +59,16 @@ _start: #else bltz t0, 1f #endif +2: li a0, 1 sw a0, tohost, t0 + j 2b 1: #ifdef __riscv_flen # initialize FPU if we have one - andi t0, t0, 1 << ('f' - 'a') - beqz t0, 1f + la t0, 1f + csrw mtvec, t0 fssr x0 fmv.s.x f0, x0 @@ -104,9 +103,12 @@ _start: fmv.s.x f29,x0 fmv.s.x f30,x0 fmv.s.x f31,x0 +1: #endif -1: + # initialize trap vector + la t0, trap_entry + csrw mtvec, t0 # initialize global pointer la gp, _gp |