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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-13 15:40:06 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-13 15:40:06 -0700 |
| commit | 33a1beb24e65c32aa8e2f2547da27eb3e24c4cc9 (patch) | |
| tree | 06a3c762fe8acd7c9096de5b00d9a5512becaf9f | |
| parent | db0b30ac92e3f5b639d0a9eda73e20cddc4e85a9 (diff) | |
| download | riscv-tests-33a1beb24e65c32aa8e2f2547da27eb3e24c4cc9.zip riscv-tests-33a1beb24e65c32aa8e2f2547da27eb3e24c4cc9.tar.gz riscv-tests-33a1beb24e65c32aa8e2f2547da27eb3e24c4cc9.tar.bz2 | |
Test mstatus.TW, mstatus.TVM, and mstatus.TSR features
| m--------- | env | 10 | ||||
| -rw-r--r-- | isa/rv64mi/illegal.S | 106 |
2 files changed, 110 insertions, 6 deletions
diff --git a/env b/env -Subproject 00d8922398c202c13d6eb5da07e92be6364309a +Subproject 497efbd0fa104b70f058ea550ed0c7f8a554662 diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S index 30c22b2..8701a76 100644 --- a/isa/rv64mi/illegal.S +++ b/isa/rv64mi/illegal.S @@ -14,10 +14,75 @@ RVTEST_RV64M RVTEST_CODE_BEGIN li TESTNUM, 2 +bad2: .word 0 j fail - j pass + # Skip the rest of the test if S-mode is not present. + li t0, MSTATUS_MPIE + csrc mstatus, t0 + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & ~(MSTATUS_MPP << 1)) * PRV_S + csrs mstatus, t1 + csrr t2, mstatus + and t2, t2, t0 + bne t1, t2, pass + + # Set a software interrupt pending so WFI won't stall. + csrwi mideleg, MIP_SSIP + csrwi mip, MIP_SSIP + csrwi mie, MIP_SSIP + la t0, 1f + csrw mepc, t0 + mret + +1: + # Make sure WFI doesn't trap when TW=0. + wfi +bad3: + .word 0 + j fail + +bad4: + # Make sure WFI does trap when TW=1. + wfi + j fail + + # Make sure SFENCE.VMA and sptbr don't trap when TVM=0. + sfence.vma + csrr t0, sptbr +bad5: + .word 0 + j fail + +bad6: + # Make sure SFENCE.VMA and sptbr do trap when TVM=1. + sfence.vma + j fail +bad7: + csrr t0, sptbr + j fail + + # Make sure SRET doesn't trap when TSR=0. + la t0, bad8 + csrw sepc, t0 + li t0, SSTATUS_SPP + csrs sstatus, t0 + li t0, SSTATUS_SPIE + csrc sstatus, t0 + sret +bad8: + .word 0 + j fail + + # Make sure SRET does trap when TSR=1. + la t0, 1f + csrw sepc, t0 +bad9: + sret +1: + j fail TEST_PASSFAIL @@ -26,10 +91,49 @@ mtvec_handler: csrr t0, mcause bne t0, t1, fail csrr t0, mepc + la t1, bad2 + beq t0, t1, 2f + la t1, bad3 + beq t0, t1, 3f + la t1, bad4 + beq t0, t1, 4f + la t1, bad5 + beq t0, t1, 5f + la t1, bad6 + beq t0, t1, 6f + la t1, bad7 + beq t0, t1, 7f + la t1, bad8 + beq t0, t1, 8f + la t1, bad9 + beq t0, t1, 9f + j fail +2: +4: +6: +7: addi t0, t0, 8 csrw mepc, t0 mret +3: + li t1, MSTATUS_TW + csrs mstatus, t1 + j 2b + +5: + li t1, MSTATUS_TVM + csrs mstatus, t1 + j 2b + +8: + li t1, MSTATUS_TSR + csrs mstatus, t1 + j 2b + +9: + j pass + RVTEST_CODE_END .data |