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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-20 10:54:15 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-02-20 10:54:15 -0800 |
| commit | b6f7299a2df870b14cd437c555e048dfe49a2ba9 (patch) | |
| tree | bd9d68f8207fd3e8a859781c9bac943c1f991c0a | |
| parent | 10706c544e9bca0cf2dc3867c9d3dbb77c53fa3b (diff) | |
| download | riscv-tests-b6f7299a2df870b14cd437c555e048dfe49a2ba9.zip riscv-tests-b6f7299a2df870b14cd437c555e048dfe49a2ba9.tar.gz riscv-tests-b6f7299a2df870b14cd437c555e048dfe49a2ba9.tar.bz2 | |
Fix rv64mi-p-csr on systems with FPUs
3a98ec2e306938cce07ab15e3678d670611aa66d introduced a subtle bug because
of the value of TESTNUM at the point an expected exception was taken. Fix
by moving the new tests earlier in the program.
| -rw-r--r-- | isa/rv64si/csr.S | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index d586d11..2860c8d 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -46,6 +46,9 @@ RVTEST_CODE_BEGIN #endif #endif + TEST_CASE(15, a0, 0, csrrwi a0, sscratch, 0; csrrwi a0, sscratch, 0xF); + TEST_CASE(16, a0, 0, csrw sscratch, zero; csrr a0, sscratch); + csrwi sscratch, 3 TEST_CASE( 2, a0, 3, csrr a0, sscratch); TEST_CASE( 3, a1, 3, csrrci a1, sscratch, 1); @@ -55,8 +58,6 @@ RVTEST_CODE_BEGIN TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0); TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0); TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch); - TEST_CASE(15, a0, 0, csrrwi a0, sscratch, 0; csrrwi a0, sscratch, 0xF); - TEST_CASE(16, a0, 0, csrw sscratch, zero; csrr a0, sscratch); #ifdef __MACHINE_MODE # Is F extension present? |