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| author | Tim Newsome <tim@sifive.com> | 2017-07-06 15:09:09 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-07-06 15:09:09 -0700 |
| commit | 14dfde33927bead9d08409e2d2b70c8bf5023095 (patch) | |
| tree | b2379e9f566cf572c4ec5e3a534e6ce445eae965 | |
| parent | cfe2798748bd8fa4db21124026ad4ea35e310006 (diff) | |
| parent | 0d211cd3885c2b98c4a2cfe01daff80b921e63fb (diff) | |
| download | riscv-tests-14dfde33927bead9d08409e2d2b70c8bf5023095.zip riscv-tests-14dfde33927bead9d08409e2d2b70c8bf5023095.tar.gz riscv-tests-14dfde33927bead9d08409e2d2b70c8bf5023095.tar.bz2 | |
Merge pull request #58 from riscv/fpga_reset_halt
debug: Make the 'out of reset' tests apply reset
| -rwxr-xr-x | debug/gdbserver.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 37fd698..5ac0153 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -205,6 +205,9 @@ class MemTestBlock(GdbTest): class InstantHaltTest(GdbTest): def test(self): + """Assert that reset is really resetting what it should.""" + self.gdb.command("monitor reset halt") + self.gdb.command("flushregs") assertEqual(self.target.reset_vector, self.gdb.p("$pc")) # mcycle and minstret have no defined reset value. mstatus = self.gdb.p("$mstatus") @@ -215,6 +218,8 @@ class InstantChangePc(GdbTest): def test(self): """Change the PC right as we come out of reset.""" # 0x13 is nop + self.gdb.command("monitor reset halt") + self.gdb.command("flushregs") self.gdb.command("p *((int*) 0x%x)=0x13" % self.target.ram) self.gdb.command("p *((int*) 0x%x)=0x13" % (self.target.ram + 4)) self.gdb.command("p *((int*) 0x%x)=0x13" % (self.target.ram + 8)) |