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| author | Andrew Waterman <andrew@sifive.com> | 2025-09-18 17:06:08 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2025-09-18 17:06:45 -0700 |
| commit | 9c61d29846d8521d9487a57739330f9682d5b542 (patch) | |
| tree | a5bf726db0caa3e445be7392039588f7833ddbcb | |
| parent | b4abf92e9954aaed291d0282c580f94254f9b11c (diff) | |
| download | riscv-pk-master.zip riscv-pk-master.tar.gz riscv-pk-master.tar.bz2 | |
Harts with IALIGN=16 might hardwire this medeleg bit to 0.
| -rw-r--r-- | machine/minit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/machine/minit.c b/machine/minit.c index 72f47ef..2256863 100644 --- a/machine/minit.c +++ b/machine/minit.c @@ -74,7 +74,6 @@ static void delegate_traps() uintptr_t interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP; uintptr_t mandatorily_delegable_exceptions = - (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_FETCH_PAGE_FAULT) | (1U << CAUSE_BREAKPOINT) | (1U << CAUSE_LOAD_PAGE_FAULT) | @@ -82,6 +81,7 @@ static void delegate_traps() (1U << CAUSE_USER_ECALL); uintptr_t exceptions = mandatorily_delegable_exceptions | + (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_SOFTWARE_CHECK_FAULT); write_csr(mideleg, interrupts); |