From d7d70c2719e6fe94dc9ca15aeb81cf142d597cdc Mon Sep 17 00:00:00 2001 From: Mete Balci Date: Sat, 30 Mar 2019 12:27:57 +0100 Subject: target/aarch64: a64 disassembler Add A64 (AArch64) Disassembler using Capstone framework. Change-Id: Ia92b57001843b11a818af940a468b131e42a03fd Signed-off-by: Mete Balci [Antonio Borneo: Rebased on current HEAD] Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5004 Tested-by: jenkins --- doc/openocd.texi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'doc') diff --git a/doc/openocd.texi b/doc/openocd.texi index 8c99228..317f188 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -9349,6 +9349,12 @@ target code relies on. In a configuration file, the command would typically be c However, normally it is not necessary to use the command at all. @end deffn +@deffn Command {aarch64 disassemble} address [count] +@cindex disassemble +Disassembles @var{count} instructions starting at @var{address}. +If @var{count} is not specified, a single instruction is disassembled. +@end deffn + @deffn Command {aarch64 smp} [on|off] Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger -- cgit v1.1