index
:
riscv-tools/riscv-openocd.git
FE_402_fix
__archive__
add_macos_build
autoconf
bscan_optimization
bscan_tunnel
buf_sget
build32
busy
compliance_dev
debug-log-reg-failure
deinit
dmi_read
dmstatus_version
dsp5680_build
eclipse_memory_read
eclipse_multicore_fix
examine_command
examine_unavailable_harts
examine_unavailable_harts_backup
examine_unavailable_harts_rebase
examine_unavailable_harts_squash
fence_i_fix_for_release
fix-halt-reason-after-singlestep
fix_macbuild
gd32vf103
gdb_next_port
gitignore-build
global
halt_examine
haltreq
hypervisor_translate
jlink
log_output
macbuild
macro
manual_hwbp
master
mem64
mpsse_flush
multicore
new_bscan_approach
newprogram
nohartstatus
old_fixes_and_eclipse_memory_read
old_triggers
print_port
race
rbb_cleanup
regcache
regression_test_janmat_experim
release
remove-slot_t-from-riscv-013
reset_test
reverse-resume-order
riscv
riscv-batch-cleanup
riscv-compliance
riscv-compliance-dev
s2_increment
sba_tests
set_group
static
travis-nop
update_defines
us_xds110
vector2
winbuild
wip
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
target
/
riscv
/
gdb_regs.h
Age
Commit message (
Expand
)
Author
Files
Lines
2024-03-21
[NFC] target/riscv: refactor `init_registers()`
Evgeniy Naydanov
1
-1
/
+4
2023-11-02
target/riscv: Adding register tables to make register names consistent
Anastasiya Chernikova
1
-1
/
+1
2023-04-25
target/riscv: Add constants for vsatp, hgatp
Tim Newsome
1
-0
/
+3
2023-03-16
Expose S?aia CSRs if they're on the target.
Tim Newsome
1
-0
/
+2
2023-01-10
target/riscv: added support for missing VCSR register
Parshintsev Anatoly
1
-0
/
+1
2022-11-09
Use match field for trigger (#725)
Xiang W
1
-0
/
+2
2020-08-24
Add SPDX tags for RISC-V files. (#513)
Tim Newsome
1
-0
/
+2
2020-08-24
Update encoding.h from riscv-opcodes (#514)
Tim Newsome
1
-1
/
+1
2020-02-14
Add support for vector register access (#448)
Tim Newsome
1
-0
/
+18
2019-12-10
riscv: translate virtual address to physical address. (#425)
Hsiangkai
1
-0
/
+1
2019-09-09
Fix flashing HiFive Unleashed (#402)
Tim Newsome
1
-0
/
+2
2019-07-08
RV32E support (#387)
Tim Newsome
1
-0
/
+1
2017-12-26
Conform to OpenOCD style guide.
Tim Newsome
1
-2
/
+2
2017-12-19
Give FPRs ABI names.
Tim Newsome
1
-1
/
+33
2017-12-19
Fix register names.
Tim Newsome
1
-6
/
+35
2017-09-30
Share register numbers between 0.11 and 0.13.
Tim Newsome
1
-0
/
+2
2017-07-27
Display register numbers in a more usable format.
Tim Newsome
1
-0
/
+2
2017-06-15
Fix indentation to match OpenOCD style.
Tim Newsome
1
-16
/
+16
2017-04-26
Add 64-bit and multihart support
Palmer Dabbelt
1
-0
/
+28