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path: root/src/target/riscv/debug_defines.h
AgeCommit message (Expand)AuthorFilesLines
2023-12-07Update riscv/debug_defines (to sync with riscv-debug-spec:40b9a05)Kirill Radkin1-815/+714
2023-09-22target/riscv: define register printersEvgeniy Naydanov1-156/+352
2022-07-18Update debug_defines.h. (#711)Tim Newsome1-10/+8
2022-05-25Use new debug_defines.h (#703)Tim Newsome1-932/+1442
2021-11-04Regenerated debug_defines.h and encoding.h (#659)Jan Matyas1-9/+16
2021-07-23Add support for hypervisor bits. (#631)Tim Newsome1-118/+742
2020-08-24Update debug_defines.h from riscv-debug-spec (#515)Tim Newsome1-1242/+1324
2020-08-07Fix of DMI batch scans over 64-bits (#432)Jan Matyas1-0/+1
2019-03-05Set up halt groups for SMP groups. (#353)Tim Newsome1-155/+580
2018-06-06Update debug defines to match specTim Newsome1-281/+294
2018-01-26Detect hartsellen, limiting which harts we probeTim Newsome1-56/+71
2017-12-26Conform to OpenOCD style guide.Tim Newsome1-8/+8
2017-12-21Update debug_defines to the one used with spike.Tim Newsome1-22/+48
2017-10-18Pay attention to impebreak.Tim Newsome1-51/+76
2017-09-18Make constants unsigned for clang.Tim Newsome1-369/+286
2017-09-18Try to fix some clang warnings.Tim Newsome1-1/+1
2017-07-10Use LL for 64-bit defines, as Windows is LLP64Palmer Dabbelt1-27/+27
2017-06-16Update debug_defines. Clarify debug output.Tim Newsome1-50/+58
2017-04-26Add 64-bit and multihart supportPalmer Dabbelt1-144/+53
2017-03-21BuildsPalmer Dabbelt1-360/+471
2017-02-25Update bits to latest spec.Tim Newsome1-576/+577
2017-02-15Some memory access works.Tim Newsome1-30/+45
2017-02-13Read misa during examine(), using program buffer.Tim Newsome1-27/+752
2017-02-13dbus -> dmiTim Newsome1-16/+16
2017-02-13Discover XLEN using abstract reg reads.Tim Newsome1-41/+57
2017-02-10Halt target in riscv_examine().Tim Newsome1-28/+31
2017-02-09Add debug_defines.h.Tim Newsome1-0/+630
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