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2023-07-29target: fix messages and return values of failed op because not haltedTomas Vanek1-4/+4
Lot of messages was logged as LOG_WARNING, but the operation failed immediately. Sometimes no error message was logged at all. Add missing messages, change warnings to errors. Sometimes ERROR_TARGET_INVALID was returned. Some command handlers returned ERROR_OK! Always return ERROR_TARGET_NOT_HALTED. While on it use LOG_TARGET_ERROR() whenever possible. Prefix command_print() message with 'Error:' to get closer to LOG_TARGET_ERROR() variant. Error message was not added to get() and set() methods of struct xxx_reg_type - the return value is properly checked and a message is logged by the caller in case of ERROR_TARGET_NOT_HALTED. Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: I2fe4187c6025f0038956ab387edbf3f461c69398 Reviewed-on: https://review.openocd.org/c/openocd/+/7819 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-18openocd: fix SPDX tag format for files .cAntonio Borneo1-1/+1
With the old checkpatch we cannot use the correct format for the SPDX tags in the file .c, in fact the C99 comments are not allowed and we had to use the block comment. With the new checkpatch, let's switch to the correct SPDX format. Change created automatically through the command: sed -i \ 's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \ $(find src/ contrib/ -name \*.c) Change-Id: I6da16506baa7af718947562505dd49606d124171 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7153 Tested-by: jenkins
2022-07-23openocd: src/target: replace the GPL-2.0-or-later license tagAntonio Borneo1-13/+2
Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7071 Tested-by: jenkins
2021-07-24openocd: fix simple cases of NULL comparisonAntonio Borneo1-1/+1
There are more than 1000 NULL comparisons to be aligned to the coding style. For recurrent NULL comparison it's preferable using trivial scripts in order to minimize the review effort. Patch generated automatically with the command: sed -i PATTERN $(find src/ -type f) where PATTERN is in the list: 's/(\([a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(\1)/g' Change-Id: Ida103e325d6d0600fb69c0b7a1557ee969db4417 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6350 Tested-by: jenkins
2021-07-20target/arm: rename CamelCase symbolsAntonio Borneo1-24/+24
No major cross dependencies, mostly changes internal to each file/function. Change-Id: I3f0879f0f33c6badc36a0dc60229323978a7e280 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6338 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Xiang W <wxjstz@126.com>
2021-05-22target/arm_dpm: rename 'wp_pc' as 'wp_addr'Antonio Borneo1-2/+1
The field 'wp_pc' was originally introduced in commit 55eeea7fceb6 ("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009 to contain the address of the instruction which triggered a watchpoint. Later on with commit 651b861d5d5f ("target/aarch64: Add watchpoint support") it has been reused in to hold directly the memory address that triggered a watchpoint. Rename 'wp_pc' as 'wp_addr' and change its doxygen description. While there, fix the format string to print the field. Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6204 Tested-by: jenkins Reviewed-by: Liming Sun <limings@nvidia.com>
2020-08-02target/arm11: fix memory leaks, including register cacheAntonio Borneo1-0/+9
There is no deinit_target method, so few memory allocations leak at openocd exit. Issue identified by tracking all calls to arm_dpm_setup(). Implement the method arm11_dpm_deinit() to free all the memory allocated in arm11_dpm_init() and call it in the new arm11_deinit_target(). NOT TESTED on real HW. Change-Id: Icab86e290fc2db14f70eb84c8286357aadb02a35 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5694 Tested-by: jenkins
2020-05-09coding style: add parenthesis around the argument of sizeofAntonio Borneo1-1/+1
The script checkpatch available in new Linux kernel offers an experimental feature for automatically fix the code in place. While still experimental, the feature works quite well for simple fixes, like parenthesis. This patch has been created automatically with the script under review for inclusion in OpenOCD, using the command: find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types SIZEOF_PARENTHESIS --fix-inplace -f {} \; Change-Id: I8adb325bdb0e13211f8bae8b4770ec1979c176bf Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5618 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2020-03-12arm: Use different enum for core_type and core_modeAntonio Borneo1-2/+2
The fields core_type and core_mode use the same enum arm_mode but encode different information, making the code less immediate to read. Use a different enum arm_core_type for the field core_type. The code behavior is not changed. Change-Id: I60f2095ea6801dfe22f6da81ec295ca71ef90466 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5258 Tested-by: jenkins
2019-03-06target/arm11: Use 'bool' data typeMarc Schink1-2/+2
Change-Id: Ia09adeab88eaf66c009f94be25ab82b0b8f88f61 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4954 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-08target/arm: add support for multi-architecture gdbAntonio Borneo1-0/+1
GDB can be built for multi-architecture through the command ./configure --enable-targets=all && make Such multi-architecture GDB requires the target's architecture to be selected either manually by the user through the GDB command "set architecture" or automatically by the target description sent by the remote target (i.e. OpenOCD). Commit e65acd889c61a424c7bd72fdee5d6a3aee1d8504 ("gdb_server: add support for architecture element") already provides the required infrastructure to support multi-architecture gdb. arm-none-eabi-gdb 8.2 uses "arm" as default architecture, but also supports the following values: "arm_any", "armv2", "armv2a", "armv3", "armv3m", "armv4", "armv4t", "armv5", "armv5t", "armv5te", "armv5tej", "armv6", "armv6k", "armv6kz", "armv6-m", "armv6s-m", "armv6t2", "armv7", "armv7e-m", "armv8-a", "armv8-m.base", "armv8-m.main", "armv8-r", "ep9312", "iwmmxt", "iwmmxt2", "xscale". These values can be displayed on arm gdb prompt by typing "set architecture " followed by a TAB for autocompletion. Set the gdb architecture value for all arm targets to "arm". Change-Id: I176cb89878606e1febd546ce26543b3e7849500a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4754 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-02-10target: Add 64-bit target address supportDongxue Zhang1-11/+11
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2016-08-09Fix resume when core state has been modifiedMatthias Welwarsky1-3/+25
Sometimes it is necessary to resume into a different state (ARM/Thumb) than at debug state entry. According to the documentation this should be possible with "arm core_state arm|thumb" before the resume command, however the original code also restores the original CPSR, which overrides whatever state the core was set to. This seems to work on some cores (e.g. Cortex-A5) but not on others (e.g. Cortex-A9). Using the "BX" instruction to set resume PC and core state works on Cortex-A9 and ARM11, but is not sufficient on Cortex-A5, where an explicit write to the PC (MOV pc, r0) is required additionally. Change-Id: Ic03153b4b250fbb8cf6c75f8e329fb34829aa35f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3386 Tested-by: jenkins Reviewed-by: Alexander Stein <alexanders83@web.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-07-19Fix usage of timeval_ms()Andreas Färber1-2/+2
First, fix the timeval_ms() implementation to not have K&R but ANSI argument semantics by adding a missing void. timeval_ms() returns an int64_t, not uint64_t or long long. Consistently use int64_t for variables and PRI*64 as format string. While at it, change a few related variables to bool for clarity. Note that timeval_ms() may return a negative error code, but not a single caller checks for that. Change-Id: I27cf83e75b3e9a8913f6c43e98a281bea77aac13 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3499 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-05target: improve robustness of reset commandTomas Vanek1-14/+25
Before this change jim_target_reset() checked examined state of a target and failed without calling .assert_reset in particular target layer (and without comprehensible warning to user). Cortex-M target (which refuses access to DP under active SRST): If connection is lost then reset process fails before asserting SRST and connection with MCU is not restored. This resulted in: 1) A lot of Cortex-M MCUs required use of reset button or cycling power after firmware blocked SWD access somehow (sleep, misconfigured clock etc). If firmware blocks SWD access early during initialization, a MCU could become completely inaccessible by SWD. 2) If OpenOCD is (re)started and a MCU is in a broken state unresponsive to SWD, reset command does not work even if it could help to restore communication. Hopefully this scenario is not possible under full JTAG. jim_target_reset() in target.c now does not check examined state and delegates this task to a particular target. All targets have been checked and xx_assert_reset() (or xx_deassert_reset()) procedures were changed to check examined state if needed. Targets except arm11, cortex_a and cortex_m just fail if target is not examined although it may be possible to use at least hw reset. Left as TODO for developers familiar with these targets. cortex_m_assert_reset(): memory access errors are stored instead of immediate returning them to a higher level. Errors from less important reads/writes are ignored. Requested reset always leads to a configured action. arm11_assert_reset() just asserts hw reset in case of not examined target. cortex_a_assert_reset() works as usual in case of not examined target. Change-Id: I84fa869f4f58e2fa83b6ea75de84440d9dc3d929 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2606 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-03-09arm11: initialise DPM and register cache before reading DSCR for the first timePaul Fertser1-6/+6
When target was already halted during the initial examination, arm11_check_init() was trying to read, store and interpret DSCR contents before the DPM structure is initialised. This caused a segfault like described on http://sourceforge.net/apps/trac/openocd/ticket/65 . This is a totally untested attempt to fix this issue. Change-Id: I2fff115679a3f0023e7a88c749ccb5f045d6cf01 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2043 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-09-08target: remove unimplemented target_request_data implementationsSpencer Oliver1-11/+0
Change-Id: Ia9afa83752d17f0f56bdf3bd81f5c69d108aa5e9 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1537 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-09-08target: remove unimplemented soft_reset_halt implementationsSpencer Oliver1-8/+0
Let the default handler issue an unsupported warning rather than using empty handler routines that may/may not issue a unsupported warning. Change-Id: Iafe3e45146981a4cfae39771c3ab7370ac86da48 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1535 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com>
2013-06-05update files to correct FSF addressSpencer Oliver1-1/+1
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-04-28arm: fix arm reg regressionSpencer Oliver1-0/+1
Seems commit fc2abe63fd3cea7497da7be2955d333bd3f800b9 caused a regression in that the arm reg cmd no longer worked. The issue was caused because we changed the value of ARM_MODE_THREAD which was being checked in arm_init_arch_info. Change-Id: Id571d4ab336d1b0e2b93363147af245d24b65ca5 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1362 Tested-by: jenkins Reviewed-by: Luca Bruno <lucab@debian.org> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-03-15target: Add default implementation of bulk_write_memoryAndreas Fritiofson1-14/+0
Remove dummy implementations from all targets except arm7_9 and mips, which are the only ones with real implementations. Replace with a single default implementation simply calling target_write_memory(). Change-Id: I9228104240bc0b50661be20bc7909713ccda2164 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1213 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-02-06build: cleanup src/target directorySpencer Oliver1-308/+259
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-01-18cmd: add missing usage varsSpencer Oliver1-0/+2
we should have caught them all - hopefully. Change-Id: I35435317fccaf5ad0216244d69f76db6857bb582 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/381 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2011-11-02arm11: print next address to debugØyvind Harboe1-2/+2
fixes clang warning. Basically the next address pointer is not used for anything in the fn, except to be examined in debug. Change-Id: I253519b8e49e54490bbe7da8ec3d2dd31f49052a Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/155 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2011-04-01types: write memory now uses constØyvind Harboe1-3/+3
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2011-01-03error handling: the error number is not part of the user interfaceØyvind Harboe1-1/+1
Do not propagate error number to user. This is for internal programming purposes only. Error messages to the user is reported as text via LOG_ERROR(). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-09-20warnings: fix alignment warningsØyvind Harboe1-2/+2
These warnings are for architectures that do not support non-aligned word access. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-07-20arm11 error propagation fixesØyvind Harboe1-23/+23
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-07-19debug: debug entry error propagationØyvind Harboe1-1/+1
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-03-08jtag: retire tap fieldØyvind Harboe1-4/+4
jtag_add_dr/ir_scan() now takes the tap as the first argument, rather than for each of the fields passed in. The code never exercised the path where there was more than one tap being scanned, who knows if it even worked. This simplifies the implementation and reduces clutter in the calling code. use jtag_add_ir/dr_plain_scan() for more fancy situations. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-02-21ARM: keep a handle to the PCDavid Brownell1-1/+1
Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21ARM11: per-core options should not be globalDavid Brownell1-33/+32
Address some FIXME comments by getting rid of globals, moving per-core parameters in the existing per-core data structure. This will matter most whenever there are multiple ARM11 cores, e.g. ARM11 MPcore chips, but in general is just cleanup. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-01-25core arm11: Silence logs at level 3 if there is no activityEdgar Grimberg1-1/+1
If the target and openocd are idling, the log should normally be silent at level 3. (Given no verbose logging options.) Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-01-22ARM11: fix breakpoints with GDBDavid Brownell1-9/+15
This fixes a bug whereby GDB's breakpoints weren't activated. The root cause is a confused interface to resume(). Fix by almost ignoring the "handle breakpoints" parameter; it only seems related to the case of skipping breakpoint-at-PC. Update a few coments to clarify what's happening. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-01-07ARM11: help/usage updatesDavid Brownell1-12/+17
Usage syntax messages have the same EBNF as the User's Guide; there should be no angle brackets in either place. Uupdate some helptext to be more accurate. Fix the User's Guide in a few places to be more consistent (mostly to use brackets not parentheses) and to recognize that parameter may be entirely optional (in which case the command just displays output, and changes nothing). Also reference NXP, not Philips, for LPC chips. Don't use "&function"; functions are like arrays, their address is their name. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-20ARM11: recognize ARM11 MPCoreDavid Brownell1-5/+11
And add my copyright. MPCore is untested, but it's the only other ARM11 core to care about. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-14ARM11: improved reset supportDavid Brownell1-48/+55
Teach ARM11 how to use: - the new "reset-assert" event - vector catch to implement "reset halt" - use SRST more like other cores do - ... including leaving post-SRST delays up to config scripts This gives OMAP2420 the ability to reset, and doesn't seem to cause new iMX31 problems. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-11ARM11: minor cleanup, mostly ITR commentsDavid Brownell1-15/+13
ITR register handling seemed to be giving me problems, so I updated the comments to better say what the code is trying to do ... and to note the preconditions (one of which seems to be an issue) as listed in the ARM1136 TRM. Also removed the unused "ARM11_TAP_DEFAULT" from the ITR scan code; all the callers already specify an exit path, since this register isn't usable with such vague semantics. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: rename some generic routinesDavid Brownell1-3/+3
Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: move opcode macros to <target/arm_opcodes.h>David Brownell1-0/+1
Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM11: report watchpoint trigger insnDavid Brownell1-0/+18
As with Cortex-A8, the WFAR register holds useful information that should be recorded and, where relevant, displayed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM11: basic watchpoint supportDavid Brownell1-1/+2
Use the DPM watchpoint support; remove old incomplete stubs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM11: tweak TAP ops and debuggingDavid Brownell1-2/+3
Tweak scanchain 7 debug messaging: - show register addresses in decimal, matching ARM docs; - remove some pointless noise Avoid some needless roundtrips: - skip SCAN_N when SCREG already holds that number (speeds up polling and other common operations) - avoid zeroing vcr twice on resume Show the IR opcode as a label ("RESTART") too; and in decimal, matching ARM docs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03ARM DPM: share debug reason logicDavid Brownell1-17/+7
No point in both ARM11 and Cortex-A8 having private copies of the logic sorting out e.g. DBG_REASON_WATCHPOINT. Add and use a shared routine for this ... there's actually a bunch more debug entry logic that could be shared, this is just a start on that. Note that this routine fixes a bug observed in the ARM11 code, where some abort mode quirks were displayed as being an unknown debug reason; and also silences needless ARM11 chatter. Likewise with private copies of DSCR ... add one to the DPM struct. Save it as part of setting DBG_REASON_* so later patches can switch over to using that copy. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03ARM11: use shared DSCR bit namesDavid Brownell1-20/+22
For the bits now defined in "arm_dpm.h", switch to the shared DSCR_* symbol and remove the ARM11_DSCR_* version. Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_* sibling symbol. (Note: for both ARM11 and Cortex-A8, this should arguably be enabled by default when single stepping.) Remove some other unused declarations in "arm11.h". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03change #include "time_support.h" to <helper/time_support.h>Zachary T Welch1-1/+1
Changes from the flat namespace to heirarchical one. Instead of writing: #include "time_support.h" the following form should be used. #include <helper/time_support.h> The exception is from .c files in the same directory.
2009-12-02ARM11: don't expose DSCRDavid Brownell1-171/+7
Remove the remaining extra copy of DSCR, and the register cache of which it was a part. That cache wasn't a very safe, or even necessary, idea; it was essentialy letting debugger-private state be manipulated by Tcl code that couldn't know how to do it right. This makes the "reg" output of an ARM11 resemble what most other ARM cores produce ... forward motion in the "make ARM11 work like the rest of the ARM cores" Jihad!
2009-12-02ARM11: store a clean copy of DSCRDavid Brownell1-59/+41
Just store a clean copy of DSCR in the per-CPU struct, so we trivially pass a pointer to a recent copy. This replaces the previous "last_dscr" and cleans up most of the related calling conventions ... but it doesn't remove the other DSCR copy.
2009-12-02ARM11: don't expose WDTRDavid Brownell1-13/+7
Don't expose the WDTR register through the register cache any more. If anyone wants Tcl scripts to be able to use DCC based communication with app code in the target, this wouldn't do it. Bugfix: don't trust the Tcl-accessible version of DSCR to flag whether WDTR needs to be restored when resuming.
generated by cgit v1.1 at 2024-09-27 18:30:53 +0000