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| author | Tarek BOCHKATI <tarek.bouchkati@gmail.com> | 2019-11-27 19:10:34 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2019-12-07 13:07:00 +0000 |
| commit | 678fb4f60b685ed79d35272bc515891fa53b527e (patch) | |
| tree | 9773b59504089f4dafeefa1672c69a9553b64cc8 /tcl/board/st_nucleo_h745zi.cfg | |
| parent | 80f1a92bd7989bfdd8b7f00d947149b77407e15c (diff) | |
| download | riscv-openocd-678fb4f60b685ed79d35272bc515891fa53b527e.zip riscv-openocd-678fb4f60b685ed79d35272bc515891fa53b527e.tar.gz riscv-openocd-678fb4f60b685ed79d35272bc515891fa53b527e.tar.bz2 | |
target/stm32h7x: add support of dual core variant of STM32H7
STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4
The second core creation is only done when
* DUAL_CORE variable is set to true
* non HLA interface is used
A second check for the second core existence is done in cpu1 examine-end
Once the second core is detected it gets examined.
Furthermore, the script provides a configurable CTI usage in order to halt
the cores simultaneously.
Tested on Rev X and V devices.
PS: the indentation was a mix of spaces and tabs, all changed to tabs.
Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5130
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'tcl/board/st_nucleo_h745zi.cfg')
| -rw-r--r-- | tcl/board/st_nucleo_h745zi.cfg | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tcl/board/st_nucleo_h745zi.cfg b/tcl/board/st_nucleo_h745zi.cfg new file mode 100644 index 0000000..bb8a396 --- /dev/null +++ b/tcl/board/st_nucleo_h745zi.cfg @@ -0,0 +1,16 @@ +# This is an ST NUCLEO-H745ZI-Q board with single STM32H745ZITx chip. + +source [find interface/stlink.cfg] +transport select hla_swd + +# ST-Link HLA interface do not support multi-AP debugging +# then setting DUAL_CORE and USE_CTI has no effect, because +# it will fall back to single core configuration +set DUAL_CORE 1 +set USE_CTI 1 + +source [find target/stm32h7x_dual_bank.cfg] + +# when using ST-Link HLA adapter, DBGMCU accesses are done via AP0 +# unfortunately DBGMCU is not accessible when SRST is asserted +reset_config srst_only |