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| author | Tarek BOCHKATI <tarek.bouchkati@gmail.com> | 2021-01-12 20:11:11 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2021-05-11 06:30:29 +0100 |
| commit | 5d9de1c40090d81288adc85d06c734984b2c5de1 (patch) | |
| tree | 2d826f84936abc286c56322830a1163db4306a33 /src/target/armv7m.h | |
| parent | aa952a1b773b65e8f469a5c04600b46e4f37a701 (diff) | |
| download | riscv-openocd-5d9de1c40090d81288adc85d06c734984b2c5de1.zip riscv-openocd-5d9de1c40090d81288adc85d06c734984b2c5de1.tar.gz riscv-openocd-5d9de1c40090d81288adc85d06c734984b2c5de1.tar.bz2 | |
cortex_m: add armv8m special registers
Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6016
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'src/target/armv7m.h')
| -rw-r--r-- | src/target/armv7m.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 652dbe7..588470f 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -60,7 +60,18 @@ enum { ARMV7M_REGSEL_MSP, ARMV7M_REGSEL_PSP, + ARMV8M_REGSEL_MSP_NS = 0x18, + ARMV8M_REGSEL_PSP_NS, + ARMV8M_REGSEL_MSP_S, + ARMV8M_REGSEL_PSP_S, + ARMV8M_REGSEL_MSPLIM_S, + ARMV8M_REGSEL_PSPLIM_S, + ARMV8M_REGSEL_MSPLIM_NS, + ARMV8M_REGSEL_PSPLIM_NS, + ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14, + ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S = 0x22, + ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS = 0x23, ARMV7M_REGSEL_FPSCR = 0x21, /* 32bit Floating-point registers */ @@ -129,6 +140,8 @@ enum { /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */ + /* A block of container and contained registers follows: + * THE ORDER IS IMPORTANT to the end of the block ! */ /* working register for packing/unpacking special regs, hidden from gdb */ ARMV7M_PMSK_BPRI_FLTMSK_CTRL, @@ -142,6 +155,35 @@ enum { ARMV7M_BASEPRI, ARMV7M_FAULTMASK, ARMV7M_CONTROL, + /* The end of block of container and contained registers */ + + /* ARMv8-M specific registers */ + ARMV8M_MSP_NS, + ARMV8M_PSP_NS, + ARMV8M_MSP_S, + ARMV8M_PSP_S, + ARMV8M_MSPLIM_S, + ARMV8M_PSPLIM_S, + ARMV8M_MSPLIM_NS, + ARMV8M_PSPLIM_NS, + + /* A block of container and contained registers follows: + * THE ORDER IS IMPORTANT to the end of the block ! */ + ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, + ARMV8M_PRIMASK_S, + ARMV8M_BASEPRI_S, + ARMV8M_FAULTMASK_S, + ARMV8M_CONTROL_S, + /* The end of block of container and contained registers */ + + /* A block of container and contained registers follows: + * THE ORDER IS IMPORTANT to the end of the block ! */ + ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, + ARMV8M_PRIMASK_NS, + ARMV8M_BASEPRI_NS, + ARMV8M_FAULTMASK_NS, + ARMV8M_CONTROL_NS, + /* The end of block of container and contained registers */ /* 64bit Floating-point registers */ ARMV7M_D0, @@ -170,6 +212,8 @@ enum { ARMV7M_CORE_LAST_REG = ARMV7M_xPSR, ARMV7M_FPU_FIRST_REG = ARMV7M_D0, ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR, + ARMV8M_FIRST_REG = ARMV8M_MSP_NS, + ARMV8M_LAST_REG = ARMV8M_CONTROL_NS, }; enum { |