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| author | Steven Stallion <stallion@squareup.com> | 2017-05-01 14:38:35 -0500 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-10-16 11:57:53 +0100 |
| commit | b5964191f0d2fc3ace607af001df3d57cbfbaf2b (patch) | |
| tree | 67ae56c1524f8816903126ff5b89b17c991d8d39 /src/rtos/uCOS-III.c | |
| parent | 06589d2de48556f5216e3e671e656f4fd9069b43 (diff) | |
| download | riscv-openocd-b5964191f0d2fc3ace607af001df3d57cbfbaf2b.zip riscv-openocd-b5964191f0d2fc3ace607af001df3d57cbfbaf2b.tar.gz riscv-openocd-b5964191f0d2fc3ace607af001df3d57cbfbaf2b.tar.bz2 | |
register: support non-existent registers
This patch fixes a number of bugs caused by incomplete support for
non-existent registers. This is needed for targets that provide optional
registers or non-linear register numbers.
Change-Id: I216196e0051f28887a2c3da410959382369eed80
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4113
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/rtos/uCOS-III.c')
0 files changed, 0 insertions, 0 deletions