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| author | Markus Reiter <me@reitermark.us> | 2022-04-16 19:04:50 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-04-23 09:24:49 +0000 |
| commit | 7ca770cbf9ecda1fe603379f6973a70ec9e913a7 (patch) | |
| tree | 94cc99a51f1a307fa38b1046cbd6ab4d9a96bbf1 | |
| parent | d47aaf6d92788efc90c6d3379d58132e7ddfa781 (diff) | |
| download | riscv-openocd-7ca770cbf9ecda1fe603379f6973a70ec9e913a7.zip riscv-openocd-7ca770cbf9ecda1fe603379f6973a70ec9e913a7.tar.gz riscv-openocd-7ca770cbf9ecda1fe603379f6973a70ec9e913a7.tar.bz2 | |
tcl/target/stm32l4x: switch to new TPIU/SWO support
Change-Id: I3362fa7292eae7a3ba119cf6183f8bc4cbd5cbd4
Signed-off-by: Markus Reiter <me@reitermark.us>
Reviewed-on: https://review.openocd.org/c/openocd/+/6932
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | tcl/target/stm32l4x.cfg | 40 |
1 files changed, 33 insertions, 7 deletions
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg index 103d741..dec2b27 100644 --- a/tcl/target/stm32l4x.cfg +++ b/tcl/target/stm32l4x.cfg @@ -38,6 +38,8 @@ if { [info exists CPUTAPID] } { swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + if {[using_jtag]} { jtag newtap $_CHIPNAME bs -irlen 5 } @@ -88,6 +90,37 @@ if {![using_hla]} { cortex_m reset_config sysresetreq } +proc proc_post_enable {_chipname} { + targets $_chipname.cpu + + if { [$_chipname.tpiu cget -protocol] eq "sync" } { + switch [$_chipname.tpiu cget -port-width] { + 1 { + mmw 0xE0042004 0x00000060 0x000000c0 + mmw 0x48001020 0x00000000 0x0000ff00 + mmw 0x48001000 0x000000a0 0x000000f0 + mmw 0x48001008 0x000000f0 0x00000000 + } + 2 { + mmw 0xE0042004 0x000000a0 0x000000c0 + mmw 0x48001020 0x00000000 0x000fff00 + mmw 0x48001000 0x000002a0 0x000003f0 + mmw 0x48001008 0x000003f0 0x00000000 + } + 4 { + mmw 0xE0042004 0x000000e0 0x000000c0 + mmw 0x48001020 0x00000000 0x0fffff00 + mmw 0x48001000 0x00002aa0 0x00003ff0 + mmw 0x48001008 0x00003ff0 0x00000000 + } + } + } else { + mmw 0xE0042004 0x00000020 0x000000c0 + } +} + +$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME" + $_TARGETNAME configure -event reset-init { # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz). # Use MSI 24 MHz clock, compliant even with VOS == 2. @@ -111,10 +144,3 @@ $_TARGETNAME configure -event examine-end { # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP mmw 0xE0042008 0x00001800 0 } - -$_TARGETNAME configure -event trace-config { - # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync - # change this value accordingly to configure trace pins - # assignment - mmw 0xE0042004 0x00000020 0 -} |