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# format of a line in this file:
# <instruction name> <args> <opcode>
#
# <opcode> is given by specifying one or more range/value pairs:
# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
#
# <args> is one of rd, rs1, rs2, rs3, imm25, imm20, imm12, imm12lo, imm12hi,
# shamtw, shamt, rm
j imm25 6..2=0x1A 1..0=3
jal imm25 6..2=0x1B 1..0=3
jalr rd rs1 imm12 9..7=0 6..2=0x19 1..0=3
beq imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x18 1..0=3
bne imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x18 1..0=3
blt imm12hi rs1 rs2 imm12lo 9..7=4 6..2=0x18 1..0=3
bge imm12hi rs1 rs2 imm12lo 9..7=5 6..2=0x18 1..0=3
bltu imm12hi rs1 rs2 imm12lo 9..7=6 6..2=0x18 1..0=3
bgeu imm12hi rs1 rs2 imm12lo 9..7=7 6..2=0x18 1..0=3
lui rd imm20 6..2=0x0D 1..0=3
auipc rd imm20 6..2=0x05 1..0=3
addi rd rs1 imm12 9..7=0 6..2=0x04 1..0=3
slli rd rs1 21..17=0 16=0 shamt 9..7=1 6..2=0x04 1..0=3
slti rd rs1 imm12 9..7=2 6..2=0x04 1..0=3
sltiu rd rs1 imm12 9..7=3 6..2=0x04 1..0=3
xori rd rs1 imm12 9..7=4 6..2=0x04 1..0=3
srli rd rs1 21..17=0 16=0 shamt 9..7=5 6..2=0x04 1..0=3
srai rd rs1 21..17=0 16=1 shamt 9..7=5 6..2=0x04 1..0=3
ori rd rs1 imm12 9..7=6 6..2=0x04 1..0=3
andi rd rs1 imm12 9..7=7 6..2=0x04 1..0=3
add rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0C 1..0=3
sub rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0C 1..0=3
sll rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0C 1..0=3
slt rd rs1 rs2 16=0 15..10=0 9..7=2 6..2=0x0C 1..0=3
sltu rd rs1 rs2 16=0 15..10=0 9..7=3 6..2=0x0C 1..0=3
xor rd rs1 rs2 16=0 15..10=0 9..7=4 6..2=0x0C 1..0=3
srl rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0C 1..0=3
sra rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0C 1..0=3
or rd rs1 rs2 16=0 15..10=0 9..7=6 6..2=0x0C 1..0=3
and rd rs1 rs2 16=0 15..10=0 9..7=7 6..2=0x0C 1..0=3
mul rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0C 1..0=3
mulh rd rs1 rs2 16=0 15..10=1 9..7=1 6..2=0x0C 1..0=3
mulhsu rd rs1 rs2 16=0 15..10=1 9..7=2 6..2=0x0C 1..0=3
mulhu rd rs1 rs2 16=0 15..10=1 9..7=3 6..2=0x0C 1..0=3
div rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0C 1..0=3
divu rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0C 1..0=3
rem rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0C 1..0=3
remu rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0C 1..0=3
addiw rd rs1 imm12 9..7=0 6..2=0x06 1..0=3
slliw rd rs1 21..17=0 16=0 15=0 shamtw 9..7=1 6..2=0x06 1..0=3
srliw rd rs1 21..17=0 16=0 15=0 shamtw 9..7=5 6..2=0x06 1..0=3
sraiw rd rs1 21..17=0 16=1 15=0 shamtw 9..7=5 6..2=0x06 1..0=3
addw rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0E 1..0=3
subw rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0E 1..0=3
sllw rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0E 1..0=3
srlw rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0E 1..0=3
sraw rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0E 1..0=3
mulw rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0E 1..0=3
divw rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0E 1..0=3
divuw rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0E 1..0=3
remw rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0E 1..0=3
remuw rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0E 1..0=3
lb rd rs1 imm12 9..7=0 6..2=0x00 1..0=3
lh rd rs1 imm12 9..7=1 6..2=0x00 1..0=3
lw rd rs1 imm12 9..7=2 6..2=0x00 1..0=3
ld rd rs1 imm12 9..7=3 6..2=0x00 1..0=3
lbu rd rs1 imm12 9..7=4 6..2=0x00 1..0=3
lhu rd rs1 imm12 9..7=5 6..2=0x00 1..0=3
lwu rd rs1 imm12 9..7=6 6..2=0x00 1..0=3
# XXX If you add new store instructions, make sure to modify tc-riscv.c and
# elfxx-riscv.c to detect them; the split immediate is handled therein.
# search for MATCH_SW and continue this inglorious hack in the obvious way.
sb imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x08 1..0=3
sh imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x08 1..0=3
sw imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x08 1..0=3
sd imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x08 1..0=3
amoadd.w rd rs1 rs2 16..10=0 9..7=2 6..2=0x0A 1..0=3
amoswap.w rd rs1 rs2 16..10=1 9..7=2 6..2=0x0A 1..0=3
amoand.w rd rs1 rs2 16..10=2 9..7=2 6..2=0x0A 1..0=3
amoor.w rd rs1 rs2 16..10=3 9..7=2 6..2=0x0A 1..0=3
amomin.w rd rs1 rs2 16..10=4 9..7=2 6..2=0x0A 1..0=3
amomax.w rd rs1 rs2 16..10=5 9..7=2 6..2=0x0A 1..0=3
amominu.w rd rs1 rs2 16..10=6 9..7=2 6..2=0x0A 1..0=3
amomaxu.w rd rs1 rs2 16..10=7 9..7=2 6..2=0x0A 1..0=3
amoadd.d rd rs1 rs2 16..10=0 9..7=3 6..2=0x0A 1..0=3
amoswap.d rd rs1 rs2 16..10=1 9..7=3 6..2=0x0A 1..0=3
amoand.d rd rs1 rs2 16..10=2 9..7=3 6..2=0x0A 1..0=3
amoor.d rd rs1 rs2 16..10=3 9..7=3 6..2=0x0A 1..0=3
amomin.d rd rs1 rs2 16..10=4 9..7=3 6..2=0x0A 1..0=3
amomax.d rd rs1 rs2 16..10=5 9..7=3 6..2=0x0A 1..0=3
amominu.d rd rs1 rs2 16..10=6 9..7=3 6..2=0x0A 1..0=3
amomaxu.d rd rs1 rs2 16..10=7 9..7=3 6..2=0x0A 1..0=3
lr.w rd rs1 21..17=0 16=1 15..10=0 9..7=2 6..2=0x0A 1..0=3
lr.d rd rs1 21..17=0 16=1 15..10=0 9..7=3 6..2=0x0A 1..0=3
sc.w rd rs1 rs2 16=1 15..10=1 9..7=2 6..2=0x0A 1..0=3
sc.d rd rs1 rs2 16=1 15..10=1 9..7=3 6..2=0x0A 1..0=3
fence.i 31..10=ignore 9..7=1 6..2=0x0B 1..0=3
fence 31..10=ignore 9..7=2 6..2=0x0B 1..0=3
fence.v.l 31..10=ignore 9..7=4 6..2=0x0B 1..0=3
fence.v.g 31..10=ignore 9..7=5 6..2=0x0B 1..0=3
syscall 31..27=0 26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x1D 1..0=3
break 31..27=0 26..22=0 21..17=0 16..10=0 9..7=1 6..2=0x1D 1..0=3
rdcycle rd 26..22=0 21..17=0 16..10=0 9..7=4 6..2=0x1D 1..0=3
rdtime rd 26..22=0 21..17=0 16..10=1 9..7=4 6..2=0x1D 1..0=3
rdinstret rd 26..22=0 21..17=0 16..10=2 9..7=4 6..2=0x1D 1..0=3
# SUPERVISOR
mtpcr rd rs1 rs2 16..10=0 9..7=0 6..2=0x1C 1..0=3
mfpcr rd rs1 21..17=0 16..10=0 9..7=1 6..2=0x1C 1..0=3
setpcr rd rs1 imm12 9..7=2 6..2=0x1C 1..0=3
clearpcr rd rs1 imm12 9..7=3 6..2=0x1C 1..0=3
eret 31..27=0 26..22=0 21..17=0 16..10=0 9..7=4 6..2=0x1C 1..0=3
# 0x7C-0x7F are reserved for >32b instructions
fadd.s rd rs1 rs2 16..12=0 rm 8..7=0 6..2=0x14 1..0=3
fsub.s rd rs1 rs2 16..12=1 rm 8..7=0 6..2=0x14 1..0=3
fmul.s rd rs1 rs2 16..12=2 rm 8..7=0 6..2=0x14 1..0=3
fdiv.s rd rs1 rs2 16..12=3 rm 8..7=0 6..2=0x14 1..0=3
fsqrt.s rd rs1 21..17=0 16..12=4 rm 8..7=0 6..2=0x14 1..0=3
fsgnj.s rd rs1 rs2 16..12=5 11..9=0 8..7=0 6..2=0x14 1..0=3
fsgnjn.s rd rs1 rs2 16..12=6 11..9=0 8..7=0 6..2=0x14 1..0=3
fsgnjx.s rd rs1 rs2 16..12=7 11..9=0 8..7=0 6..2=0x14 1..0=3
fadd.d rd rs1 rs2 16..12=0x0 rm 8..7=1 6..2=0x14 1..0=3
fsub.d rd rs1 rs2 16..12=0x1 rm 8..7=1 6..2=0x14 1..0=3
fmul.d rd rs1 rs2 16..12=0x2 rm 8..7=1 6..2=0x14 1..0=3
fdiv.d rd rs1 rs2 16..12=0x3 rm 8..7=1 6..2=0x14 1..0=3
fsqrt.d rd rs1 21..17=0 16..12=0x4 rm 8..7=1 6..2=0x14 1..0=3
fsgnj.d rd rs1 rs2 16..12=0x5 11..9=0 8..7=1 6..2=0x14 1..0=3
fsgnjn.d rd rs1 rs2 16..12=0x6 11..9=0 8..7=1 6..2=0x14 1..0=3
fsgnjx.d rd rs1 rs2 16..12=0x7 11..9=0 8..7=1 6..2=0x14 1..0=3
fcvt.l.s rd rs1 21..17=0 16..12=0x8 rm 8..7=0 6..2=0x14 1..0=3
fcvt.lu.s rd rs1 21..17=0 16..12=0x9 rm 8..7=0 6..2=0x14 1..0=3
fcvt.w.s rd rs1 21..17=0 16..12=0xA rm 8..7=0 6..2=0x14 1..0=3
fcvt.wu.s rd rs1 21..17=0 16..12=0xB rm 8..7=0 6..2=0x14 1..0=3
fcvt.l.d rd rs1 21..17=0 16..12=0x8 rm 8..7=1 6..2=0x14 1..0=3
fcvt.lu.d rd rs1 21..17=0 16..12=0x9 rm 8..7=1 6..2=0x14 1..0=3
fcvt.w.d rd rs1 21..17=0 16..12=0xA rm 8..7=1 6..2=0x14 1..0=3
fcvt.wu.d rd rs1 21..17=0 16..12=0xB rm 8..7=1 6..2=0x14 1..0=3
fcvt.s.l rd rs1 21..17=0 16..12=0xC rm 8..7=0 6..2=0x14 1..0=3
fcvt.s.lu rd rs1 21..17=0 16..12=0xD rm 8..7=0 6..2=0x14 1..0=3
fcvt.s.w rd rs1 21..17=0 16..12=0xE rm 8..7=0 6..2=0x14 1..0=3
fcvt.s.wu rd rs1 21..17=0 16..12=0xF rm 8..7=0 6..2=0x14 1..0=3
fcvt.d.l rd rs1 21..17=0 16..12=0xC rm 8..7=1 6..2=0x14 1..0=3
fcvt.d.lu rd rs1 21..17=0 16..12=0xD rm 8..7=1 6..2=0x14 1..0=3
fcvt.d.w rd rs1 21..17=0 16..12=0xE rm 8..7=1 6..2=0x14 1..0=3
fcvt.d.wu rd rs1 21..17=0 16..12=0xF rm 8..7=1 6..2=0x14 1..0=3
fcvt.s.d rd rs1 21..17=0 16..14=0x4 13..12=1 rm 8..7=0 6..2=0x14 1..0=3
fcvt.d.s rd rs1 21..17=0 16..14=0x4 13..12=0 rm 8..7=1 6..2=0x14 1..0=3
feq.s rd rs1 rs2 16..12=0x15 11..9=0 8..7=0 6..2=0x14 1..0=3
flt.s rd rs1 rs2 16..12=0x16 11..9=0 8..7=0 6..2=0x14 1..0=3
fle.s rd rs1 rs2 16..12=0x17 11..9=0 8..7=0 6..2=0x14 1..0=3
feq.d rd rs1 rs2 16..12=0x15 11..9=0 8..7=1 6..2=0x14 1..0=3
flt.d rd rs1 rs2 16..12=0x16 11..9=0 8..7=1 6..2=0x14 1..0=3
fle.d rd rs1 rs2 16..12=0x17 11..9=0 8..7=1 6..2=0x14 1..0=3
fmin.s rd rs1 rs2 16..12=0x18 11..9=0 8..7=0 6..2=0x14 1..0=3
fmax.s rd rs1 rs2 16..12=0x19 11..9=0 8..7=0 6..2=0x14 1..0=3
fmin.d rd rs1 rs2 16..12=0x18 11..9=0 8..7=1 6..2=0x14 1..0=3
fmax.d rd rs1 rs2 16..12=0x19 11..9=0 8..7=1 6..2=0x14 1..0=3
fmv.x.s rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=0 6..2=0x14 1..0=3
fmv.x.d rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=1 6..2=0x14 1..0=3
mffsr rd 26..22=0 21..17=0 16..12=0x1D 11..9=0 8..7=0 6..2=0x14 1..0=3
fmv.s.x rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=0 6..2=0x14 1..0=3
fmv.d.x rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=1 6..2=0x14 1..0=3
mtfsr rd rs1 21..17=0 16..12=0x1F 11..9=0 8..7=0 6..2=0x14 1..0=3
flw rd rs1 imm12 9..7=2 6..2=0x01 1..0=3
fld rd rs1 imm12 9..7=3 6..2=0x01 1..0=3
fsw imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x09 1..0=3
fsd imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x09 1..0=3
fmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x10 1..0=3
fmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x11 1..0=3
fnmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x12 1..0=3
fnmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x13 1..0=3
fmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x10 1..0=3
fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3
fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3
fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3
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