From c31c18ef03646506011b568780e30fe67c7bbb6d Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 26 Jul 2013 17:46:42 -0700 Subject: Factor out Hwacha/RVC and rename MFTX/MXTF to FMV --- opcodes | 194 ++-------------------------------------------------------------- 1 file changed, 4 insertions(+), 190 deletions(-) (limited to 'opcodes') diff --git a/opcodes b/opcodes index 6f3ea29..036dd83 100644 --- a/opcodes +++ b/opcodes @@ -183,11 +183,11 @@ fmax.s rd rs1 rs2 16..12=0x19 11..9=0 8..7=0 6..2=0x14 1..0=3 fmin.d rd rs1 rs2 16..12=0x18 11..9=0 8..7=1 6..2=0x14 1..0=3 fmax.d rd rs1 rs2 16..12=0x19 11..9=0 8..7=1 6..2=0x14 1..0=3 -mftx.s rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=0 6..2=0x14 1..0=3 -mftx.d rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=1 6..2=0x14 1..0=3 +fmv.x.s rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=0 6..2=0x14 1..0=3 +fmv.x.d rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=1 6..2=0x14 1..0=3 mffsr rd 26..22=0 21..17=0 16..12=0x1D 11..9=0 8..7=0 6..2=0x14 1..0=3 -mxtf.s rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=0 6..2=0x14 1..0=3 -mxtf.d rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=1 6..2=0x14 1..0=3 +fmv.s.x rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=0 6..2=0x14 1..0=3 +fmv.d.x rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=1 6..2=0x14 1..0=3 mtfsr rd rs1 21..17=0 16..12=0x1F 11..9=0 8..7=0 6..2=0x14 1..0=3 flw rd rs1 imm12 9..7=2 6..2=0x01 1..0=3 @@ -205,189 +205,3 @@ fmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x10 1..0=3 fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3 fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3 fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3 - -# vector scalar instructions -stop 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1D 1..0=3 -utidx rd 26..22=0 21..17=0 16..10=0 9..7=3 6..2=0x1D 1..0=3 -movz rd rs1 rs2 16..10=0 9..7=5 6..2=0x1D 1..0=3 -movn rd rs1 rs2 16..10=1 9..7=5 6..2=0x1D 1..0=3 -fmovz rd rs1 rs2 16..10=2 9..7=5 6..2=0x1D 1..0=3 -fmovn rd rs1 rs2 16..10=3 9..7=5 6..2=0x1D 1..0=3 - -vxcptsave 31..27=0 rs1 21..17=0 16..10=0x0 9..7=6 6..2=0x1E 1..0=3 -vxcptrestore 31..27=0 rs1 21..17=0 16..10=0x1 9..7=6 6..2=0x1E 1..0=3 -vxcptkill 31..27=0 26..22=0 21..17=0 16..10=0x2 9..7=6 6..2=0x1E 1..0=3 - -vxcptevac 31..27=0 rs1 21..17=0 16..10=0x8 9..7=6 6..2=0x1E 1..0=3 -vxcpthold 31..27=0 26..22=0 21..17=0 16..10=0x9 9..7=6 6..2=0x1E 1..0=3 -venqcmd 31..27=0 rs1 rs2 16..10=0xA 9..7=6 6..2=0x1E 1..0=3 -venqimm1 31..27=0 rs1 rs2 16..10=0xB 9..7=6 6..2=0x1E 1..0=3 -venqimm2 31..27=0 rs1 rs2 16..10=0xC 9..7=6 6..2=0x1E 1..0=3 -venqcnt 31..27=0 rs1 rs2 16..10=0xD 9..7=6 6..2=0x1E 1..0=3 - -# vector load mem instructions - -# 3=d -# 2=seg 2=w -# 1=st 1=seg 1=f 1=s 1=h -# 0=u 0=etc 0=x 0=u 0=b -# ---------------------------------------------------------------------------- -# mem padding type seg x/f u/s width opcode -# unit stride | | | | | | | | -# xloads | | | | | | | | -vld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -vlw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -vlwu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -vlh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -vlhu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -vlb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -vlbu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 -# floads -vfld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -vflw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 - -# mem padding type seg x/f u/s width opcode -# stride | | | | | | | | -# xloads | | | | | | | | -vlstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -vlstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -vlstwu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -vlsth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -vlsthu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -vlstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -vlstbu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 -# floads -vflstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -vflstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 - -# mem padding type seg x/f u/s width opcode -# segment | | | | | | | | -# xloads | | | | | | | | -vlsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -vlsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -vlsegwu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -vlsegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -vlseghu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -vlsegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -vlsegbu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 -# floads -vflsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -vflsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 - -# seg x/f u/s width opcode -# stride segment | | | | | -# xloads | | | | | -vlsegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -vlsegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -vlsegstwu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -vlsegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -vlsegsthu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -vlsegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -vlsegstbu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3 -# floads -vflsegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -vflsegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 - -# vector store mem instructions -# mem padding type seg x/f u/s width opcode -# unit stride | | | | | | | | -# xstores | | | | | | | | -vsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -vsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 -vsh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 -vsb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 -# fstores -vfsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -vfsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 - -# mem padding type seg x/f u/s width opcode -# stride | | | | | | | | -# xstores | | | | | | | | -vsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -vsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 -vssth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 -vsstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 -# fstores -vfsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -vfsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 - -# mem padding type seg x/f u/s width opcode -# segment | | | | | | | | -# xstores | | | | | | | | -vssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -vssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 -vssegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 -vssegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 -# fstores -vfssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -vfssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 - -# seg x/f u/s width opcode -# stride segment | | | | | -# xstores | | | | | -vssegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -vssegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 -vssegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3 -vssegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3 -# fstores -vfssegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -vfssegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 - -# other vector register instructions -vmvv rd rs1 21..17=0 16..11=0 10..8=0 7=0 6..2=0x1C 1..0=3 -vmsv rd rs1 21..17=0 16..11=1 10..8=0 7=0 6..2=0x1C 1..0=3 -vmst rd rs1 rs2 16..11=2 10..8=0 7=0 6..2=0x1C 1..0=3 -vmts rd rs1 rs2 16..11=3 10..8=0 7=0 6..2=0x1C 1..0=3 -vfmvv rd rs1 21..17=0 16..11=0 10..8=1 7=0 6..2=0x1C 1..0=3 -vfmsv rd rs1 21..17=0 16..11=1 10..8=1 7=0 6..2=0x1C 1..0=3 -vfmst rd rs1 rs2 16..11=2 10..8=1 7=0 6..2=0x1C 1..0=3 -vfmts rd rs1 rs2 16..11=3 10..8=1 7=0 6..2=0x1C 1..0=3 -vvcfg 31..27=0 rs1 rs2 16..11=0 10..8=4 7=0 6..2=0x1C 1..0=3 -vtcfg 31..27=0 rs1 rs2 16..11=1 10..8=4 7=0 6..2=0x1C 1..0=3 - -# other vector immediate instructions -vvcfgivl rd rs1 imm12 9..8=0 7=1 6..2=0x1C 1..0=3 -vtcfgivl rd rs1 imm12 9..8=1 7=1 6..2=0x1C 1..0=3 -vsetvl rd rs1 21..10=0 9..8=2 7=1 6..2=0x1C 1..0=3 -vf 31..27=0 rs1 imm12 9..8=3 7=1 6..2=0x1C 1..0=3 - -# compressed instructions -c.li cimm6 crd 4..0=0 -c.addi cimm6 crd 4..0=1 -c.addiw cimm6 crd 4..0=29 -c.ldsp cimm6 crd 4..0=4 -c.lwsp cimm6 crd 4..0=5 -c.sdsp cimm6 crd 4..0=6 -c.swsp cimm6 crd 4..0=8 - -c.lw0 15=0 crs1 crd 4..0=18 -c.ld0 15=1 crs1 crd 4..0=18 -c.add 15=0 crs1 crd 4..0=26 -c.sub 15=1 crs1 crd 4..0=26 -c.move 15=0 crs1 crd 4..0=2 - -c.j 15=1 cimm10 4..0=2 - -c.ld crds crs1s cimm5 4..0=9 -c.lw crds crs1s cimm5 4..0=10 -c.sd crs2s crs1s cimm5 4..0=12 -c.sw crs2s crs1s cimm5 4..0=13 -c.beq crs2s crs1s cimm5 4..0=16 -c.bne crs2s crs1s cimm5 4..0=17 -c.flw crds crs1s cimm5 4..0=20 -c.fld crds crs1s cimm5 4..0=21 -c.fsw crs2s crs1s cimm5 4..0=22 -c.fsd crs2s crs1s cimm5 4..0=24 - -c.slli crds 12..10=0 cimm5 4..0=25 -c.slli32 crds 12..10=1 cimm5 4..0=25 -c.srli crds 12..10=2 cimm5 4..0=25 -c.srli32 crds 12..10=3 cimm5 4..0=25 -c.srai crds 12..10=4 cimm5 4..0=25 -c.srai32 crds 12..10=5 cimm5 4..0=25 -c.slliw crds 12..10=6 cimm5 4..0=25 - -c.add3 crds crs1s 9..8=0 crs2bs 4..0=28 -c.sub3 crds crs1s 9..8=1 crs2bs 4..0=28 -c.or3 crds crs1s 9..8=2 crs2bs 4..0=28 -c.and3 crds crs1s 9..8=3 crs2bs 4..0=28 -- cgit v1.1