From 03d59c5e5a732bc075a28525c1aaa0368b9144db Mon Sep 17 00:00:00 2001
From: Jiuyang Liu <liu@jiuyang.me>
Date: Sun, 24 Sep 2023 18:30:00 +0800
Subject: split arg_lut, causes, csr, csr32 from constants.py

---
 arg_lut.csv | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)
 create mode 100644 arg_lut.csv

(limited to 'arg_lut.csv')

diff --git a/arg_lut.csv b/arg_lut.csv
new file mode 100644
index 0000000..b143650
--- /dev/null
+++ b/arg_lut.csv
@@ -0,0 +1,100 @@
+"rd", 11, 7
+"rt", 19, 15
+"rs1", 19, 15
+"rs2", 24, 20
+"rs3", 31, 27
+"aqrl", 26, 25
+"aq", 26, 26
+"rl", 25, 25
+"fm", 31, 28
+"pred", 27, 24
+"succ", 23, 20
+"rm", 14, 12
+"funct3", 14, 12
+"funct2", 26, 25
+"imm20", 31, 12
+"jimm20", 31, 12
+"imm12", 31, 20
+"csr", 31, 20
+"imm12hi", 31, 25
+"bimm12hi", 31, 25
+"imm12lo", 11, 7
+"bimm12lo", 11, 7
+"shamtq", 26, 20
+"shamtw", 24, 20
+"shamtw4", 23, 20
+"shamtd", 25, 20
+"bs", 31, 30
+"rnum", 23, 20
+"rc", 29, 25
+"imm2", 21, 20
+"imm3", 22, 20
+"imm4", 23, 20
+"imm5", 24, 20
+"imm6", 25, 20
+"zimm", 19, 15
+"opcode", 6,0
+"funct7", 31,25
+"vd", 11, 7
+"vs3", 11, 7
+"vs1", 19, 15
+"vs2", 24, 20
+"vm", 25, 25
+"wd", 26, 26
+"amoop", 31, 27
+"nf", 31, 29
+"simm5", 19, 15
+"zimm5", 19, 15
+"zimm10", 29, 20
+"zimm11", 30, 20
+"zimm6hi", 26, 26
+"zimm6lo", 19, 15
+"c_nzuimm10", 12, 5
+"c_uimm7lo", 6, 5
+"c_uimm7hi", 12, 10
+"c_uimm8lo", 6, 5
+"c_uimm8hi", 12, 10
+"c_uimm9lo", 6, 5
+"c_uimm9hi", 12, 10
+"c_nzimm6lo", 6, 2
+"c_nzimm6hi", 12, 12
+"c_imm6lo", 6, 2
+"c_imm6hi", 12, 12
+"c_nzimm10hi", 12, 12
+"c_nzimm10lo", 6, 2
+"c_nzimm18hi", 12, 12
+"c_nzimm18lo", 6, 2
+"c_imm12", 12, 2
+"c_bimm9lo", 6, 2
+"c_bimm9hi", 12, 10
+"c_nzuimm5", 6, 2
+"c_nzuimm6lo", 6, 2
+"c_nzuimm6hi", 12, 12
+"c_uimm8splo", 6, 2
+"c_uimm8sphi", 12, 12
+"c_uimm8sp_s", 12, 7
+"c_uimm10splo", 6, 2
+"c_uimm10sphi", 12, 12
+"c_uimm9splo", 6, 2
+"c_uimm9sphi", 12, 12
+"c_uimm10sp_s", 12, 7
+"c_uimm9sp_s", 12, 7
+"c_uimm2", 6, 5
+"c_uimm1", 5, 5
+"c_rlist", 7, 4
+"c_spimm", 3, 2
+"c_index", 9, 2
+"rs1_p", 9, 7
+"rs2_p", 4, 2
+"rd_p", 4, 2
+"rd_rs1_n0", 11, 7
+"rd_rs1_p", 9, 7
+"rd_rs1", 11, 7
+"rd_n2", 11, 7
+"rd_n0", 11, 7
+"rs1_n0", 11, 7
+"c_rs2_n0", 6, 2
+"c_rs1_n0", 11, 7
+"c_rs2", 6, 2
+"c_sreg1", 9, 7
+"c_sreg2", 4, 2
-- 
cgit v1.1