From 9d28c9a9a173f197b1983842caae550d60b36706 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 21 Jan 2019 22:40:06 -0800 Subject: Add tentative hypervisor CSR and instruction encodings --- opcodes | 4 ++++ parse-opcodes | 20 +++++++++++++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/opcodes b/opcodes index 544c5d3..9eb137a 100644 --- a/opcodes +++ b/opcodes @@ -128,6 +128,10 @@ csrrwi rd rs1 imm12 14..12=5 6..2=0x1C 1..0=3 csrrsi rd rs1 imm12 14..12=6 6..2=0x1C 1..0=3 csrrci rd rs1 imm12 14..12=7 6..2=0x1C 1..0=3 +# Hypervisor extension +hfence.bvma 11..7=0 rs1 rs2 31..25=0x11 14..12=0 6..2=0x1C 1..0=3 +hfence.gvma 11..7=0 rs1 rs2 31..25=0x51 14..12=0 6..2=0x1C 1..0=3 + # F/D EXTENSIONS fadd.s rd rs1 rs2 31..27=0x00 rm 26..25=0 6..2=0x14 1..0=3 fsub.s rd rs1 rs2 31..27=0x01 rm 26..25=0 6..2=0x14 1..0=3 diff --git a/parse-opcodes b/parse-opcodes index c34c1c6..9881801 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -105,6 +105,21 @@ csrs = [ (0x144, 'sip'), (0x180, 'satp'), + # Standard Hypervisor R/w + (0x200, 'bsstatus'), + (0x204, 'bsie'), + (0x205, 'bstvec'), + (0x240, 'bsscratch'), + (0x241, 'bsepc'), + (0x242, 'bscause'), + (0x243, 'bstval'), + (0x244, 'bsip'), + (0x280, 'bsatp'), + (0xA00, 'hstatus'), + (0xA02, 'hedeleg'), + (0xA03, 'hideleg'), + (0xA80, 'hgatp'), + # Standard Machine R/W (0x300, 'mstatus'), (0x301, 'misa'), @@ -736,8 +751,11 @@ def make_supervisor_latex_table(): print_insts('uret', 'sret', 'mret') print_subtitle('Interrupt-Management Instructions') print_insts('wfi') - print_subtitle('Memory-Management Instructions') + print_subtitle('Supervisor Memory-Management Instructions') print_insts('sfence.vma') + print_subtitle('Hypervisor Memory-Management Instructions') + print_insts('hfence.bvma') + print_insts('hfence.gvma') print_footer('\\caption{RISC-V Privileged Instructions}') def make_latex_table(): -- cgit v1.1