From 9780234be4e34702f69d7bcce503f488cf14b327 Mon Sep 17 00:00:00 2001 From: "Tsukasa #01 (a4lg)" Date: Fri, 21 Jan 2022 06:34:13 +0900 Subject: Synchronize priv-instr-table.tex with the Manual (#99) This commit roughly synchronizes privileged instruction table with the ISA Manual with slight instruction order modifications, expecting instruction tables in the ISA Manual are fully generated by riscv-opcodes, not modified by hand. This is based on: * riscv/riscv-isa-manual: commit f30a5f6de685 ("Update chapters 2 and 7 for Hypervisor v0.6") * riscv/riscv-opcodes: commit 65af4131c26f ("Virtual memory updates (#76)") --- parse_opcodes | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/parse_opcodes b/parse_opcodes index a29180f..5f2ebb8 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -901,14 +901,21 @@ def make_supervisor_latex_table(): print_subtitle('Supervisor Memory-Management Instructions') print_insts('sfence.vma') print_subtitle('Hypervisor Memory-Management Instructions') - print_insts('hfence.vvma') - print_insts('hfence.gvma') - print_subtitle('Svinval Memory-Management Instructions') + print_insts('hfence.vvma', 'hfence.gvma') + print_subtitle('Hypervisor Virtual-Machine Load and Store Instructions') + print_insts('hlv.b', 'hlv.bu') + print_insts('hlv.h', 'hlv.hu') + print_insts('hlv.w') + print_insts('hlvx.hu', 'hlvx.wu') + print_insts('hsv.b', 'hsv.h', 'hsv.w') + print_subtitle('Hypervisor Virtual-Machine Load and Store Instructions, RV64 only') + print_insts('hlv.wu') + print_insts('hlv.d') + print_insts('hsv.d') + print_subtitle('\emph{Svinval} Memory-Management Extension') print_insts('sinval.vma') - print_insts('sfence.w.inval') - print_insts('sfence.inval.ir') - print_insts('hinval.vvma') - print_insts('hinval.gvma') + print_insts('sfence.w.inval', 'sfence.inval.ir') + print_insts('hinval.vvma', 'hinval.gvma') print_footer('\\caption{RISC-V Privileged Instructions}') def make_latex_table(): -- cgit v1.1