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AgeCommit message (Expand)AuthorFilesLines
2016-06-01Add dret instruction and debug CSRs. (#5)Tim Newsome1-0/+1
2016-04-30ERET -> xRETAndrew Waterman1-2/+5
2016-02-05WIP on priv spec v1.9Andrew Waterman1-6/+3
2015-05-09Update to privileged architecture version 1.7Andrew Waterman1-0/+3
2015-03-17Merge [shm]call into ecall, [shm]ret into eretAndrew Waterman1-6/+3
2015-03-12Add hcall instructionAndrew Waterman1-0/+1
2015-03-12Update to new privileged specAndrew Waterman1-9/+13
2014-03-11New FP encodingAndrew Waterman1-69/+65
2014-03-06Add fclass.{s|d} instructionsAndrew Waterman1-4/+6
2014-01-13swap JAL/JALR againAndrew Waterman1-5/+5
2013-11-25New privileged ISAAndrew Waterman1-36/+35
2013-11-21fix slli/slliw encoding bugYunsup Lee1-2/+2
2013-09-21Update ISA encodingAndrew Waterman1-186/+181
2013-08-06Rename MTFSR/MFFSR to FSSR/FRSRAndrew Waterman1-2/+2
2013-07-31HW ignores upper bits of fence, but SW supplies 0Andrew Waterman1-4/+4
2013-07-31Swap J and JALR encodingsAndrew Waterman1-2/+2
2013-07-26change supervisor encodingYunsup Lee1-5/+5
2013-07-26Factor out Hwacha/RVC and rename MFTX/MXTF to FMVAndrew Waterman1-190/+4
2013-07-25Refactor parse-opcodesAndrew Waterman1-25/+27
2013-07-25Remove JALR static hintsAndrew Waterman1-3/+1
2013-07-23Remove CFLUSHAndrew Waterman1-1/+0
2013-04-17add auipc, lr, scAndrew Waterman1-1/+6
2012-03-24new supervisor modeAndrew Waterman1-18/+17
2012-03-18change vector fence names/encodingAndrew Waterman1-8/+4
2012-03-18clean up vector exception instructionsYunsup Lee1-7/+10
2012-03-13add more instructions for vector exception handlingYunsup Lee1-1/+5
2012-03-13add vvcfg,vtcfgYunsup Lee1-0/+2
2012-03-13opcodes cleanupYunsup Lee1-7/+6
2012-03-10slight change to vector supervisor instructionsYunsup Lee1-4/+4
2012-03-03new instructions to handle vector exceptionsYunsup Lee1-0/+6
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+380
2011-06-19Renamed packagesAndrew Waterman1-380/+0
2011-05-15[opcodes,pk,sim,xcc] resolve a conflictYunsup Lee1-6/+6
2011-05-15[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsYunsup Lee1-89/+107
2011-05-13tweaked encoding of rdcycle & cousinsAndrew Waterman1-5/+8
2011-05-06[opcodes] reordered RVC instructionsAndrew Waterman1-13/+14
2011-04-24[xcc,sim,opcodes] added c.addiwAndrew Waterman1-0/+2
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman1-4/+26
2011-04-18[xcc,sim,opcodes] added rvc conditional branchesAndrew Waterman1-12/+14
2011-04-12[xcc,pk,sim] added privileged cflush instructionAndrew Waterman1-0/+1
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman1-4/+12
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-2/+4
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman1-1/+2
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman1-5/+6
2011-04-06[opcodes,pk,sim,xcc] fix utidx - add rdYunsup Lee1-1/+1
2011-04-05[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Yunsup Lee1-43/+113
2011-04-04[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Yunsup Lee1-0/+6
2011-04-04[opcodes,pk,sim,xcc] add vector mem instructionsYunsup Lee1-0/+38
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee1-0/+2
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee1-2/+6
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