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AgeCommit message (Collapse)AuthorFilesLines
2015-09-02Remove automatically-generated filesAndrew Waterman1-2030/+0
2014-03-18Add rdcycleh etc. for RV32Andrew Waterman1-28/+42
2014-03-11New FP encodingAndrew Waterman1-185/+235
2014-03-06Add fclass.{s|d} instructionsAndrew Waterman1-36/+56
2014-01-13swap JAL/JALR againAndrew Waterman1-2/+2
2013-12-09New RDCYCLE encodingAndrew Waterman1-22/+22
2013-11-25New privileged ISAAndrew Waterman1-23/+63
2013-11-22add missing imm for storesYunsup Lee1-6/+6
2013-11-21fix slli/slliw encoding bugYunsup Lee1-2/+2
2013-10-29changes to the instr-tableYunsup Lee1-31/+69
2013-09-21Fix funct field in tables.Andrew Waterman1-52/+52
2013-09-21Update ISA encodingAndrew Waterman1-866/+845
2013-08-06Rename MTFSR/MFFSR to FSSR/FRSRAndrew Waterman1-2/+2
2013-07-31HW ignores upper bits of fence, but SW supplies 0Andrew Waterman1-8/+10
2013-07-31Swap J and JALR encodingsAndrew Waterman1-2/+2
2013-07-26tweaksYunsup Lee1-65/+87
2013-07-26Factor out Hwacha/RVC and rename MFTX/MXTF to FMVAndrew Waterman1-4/+4
2013-07-25Refactor parse-opcodesAndrew Waterman1-798/+531
2013-04-17add auipc, lr, scAndrew Waterman1-9/+40
2012-03-18change vector fence names/encodingAndrew Waterman1-20/+2
2012-03-13opcodes cleanupYunsup Lee1-4/+4
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+2119
2011-06-19Renamed packagesAndrew Waterman1-2119/+0
2011-05-15[opcodes,pk,sim,xcc] resolve a conflictYunsup Lee1-6/+6
2011-05-15[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsYunsup Lee1-0/+40
2011-05-13tweaked encoding of rdcycle & cousinsAndrew Waterman1-6/+36
2011-04-06[opcodes,pk,sim,xcc] fix utidx - add rdYunsup Lee1-2/+2
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee1-0/+20
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee1-0/+36
2011-03-25[opcodes] fixed up instruction tableAndrew Waterman1-1268/+1277
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman1-13/+94
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman1-77/+43
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman1-54/+0
in rv32 these will be replaced with loads and stores.
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman1-4/+22
2011-02-02[opcodes,pk,sim,xcc] synci now bombs whole icacheAndrew Waterman1-9/+9
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman1-33/+15
- Added 5th rounding mode - Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...) - merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode - made MFFL.D and MFFH.D illegal in RV64
2011-01-25[sim,opcodes] add mulhsu instructionAndrew Waterman1-0/+9
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman1-62/+60
2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman1-577/+97
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-18/+0
now generic variants behave differently in RV32 and RV64.
2011-01-17[opcodes, pk, sim, xcc] removed nor, normalized macros to addiAndrew Waterman1-9/+0
2011-01-03[opcodes,pk,sim,xcc] flip fields to favor little endianYunsup Lee1-556/+1117
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman1-782/+544
2010-11-21[opcodes] generate latex and verilog correctlyAndrew Waterman1-855/+933
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman1-479/+398
2010-11-21[opcodes, pk, sim, xcc] made jumps shorter and PC-relativeAndrew Waterman1-8/+2
2010-10-31[opcodes] add latex table for rm stuffYunsup Lee1-464/+930
2010-10-25[sim,xcc,pk,opcodes] static rounding modes for FP insnsAndrew Waterman1-88/+16
Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.)
2010-10-20[opcodes] changed formatting of optab section headersAndrew Waterman1-6/+6
2010-10-15[pk, sim] added FPU emulation support to proxy kernelAndrew Waterman1-1/+1
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