riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2010-10-07	[xcc] modified opcodes for better FP decode mapping	Andrew Waterman	1	-7/+7

2010-10-05	[opcodes] added code field back to syscall/break	Andrew Waterman	1	-2/+2

2010-10-05	[opcodes] updated parse-opcodes for latex tables	Yunsup Lee	1	-216/+266

2010-10-05	[opcodes] update parse-opcodes	Yunsup Lee	1	-307/+289

2010-10-02	[xcc, sim] mff now uses rs2 for data	Andrew Waterman	1	-39/+39
	this is symmetric with fp stores, so we only need one decoding pipe
2010-09-28	[opcodes, sim, xcc] added mffl.d instruction	Andrew Waterman	1	-274/+265
	...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu
2010-09-20	[xcc, sim] changed instruction format so imm12 subs for rs2	Andrew Waterman	1	-408/+408

2010-09-13	[xcc, sim] replaced ble/bleu with bge/bgeu	Andrew Waterman	1	-7/+7
	This will simplify control logic (since every branch has a logical inverse)
2010-09-12	[opcodes] fixed tex table for ish,ishw types	Yunsup Lee	1	-96/+86

2010-09-12	[sim] renamed sllv to sll (same for other shifts)	Andrew Waterman	1	-6/+6

2010-09-12	[xcc, sim] moved shamt field and renamed shifts	Andrew Waterman	1	-98/+98

2010-09-12	[xcc, sim] branches now are next-PC-based, not PC-based	Andrew Waterman	1	-1/+1

2010-09-10	[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit	Andrew Waterman	1	-2/+2

2010-09-10	[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)	Yunsup Lee	1	-0/+18

2010-09-10	[opcodes] latex table generation added, new opcode mapping	Yunsup Lee	1	-0/+1752